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Side by Side Diff: src/compiler/mips/instruction-codes-mips.h

Issue 1510493002: MIPS: [turbofan] Combine ChangeFloat64ToInt32 with Float64Round ops. (Closed) Base URL: https://chromium.googlesource.com/v8/v8.git@master
Patch Set: Created 5 years ago
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1 // Copyright 2014 the V8 project authors. All rights reserved. 1 // Copyright 2014 the V8 project authors. All rights reserved.
2 // Use of this source code is governed by a BSD-style license that can be 2 // Use of this source code is governed by a BSD-style license that can be
3 // found in the LICENSE file. 3 // found in the LICENSE file.
4 4
5 #ifndef V8_COMPILER_MIPS_INSTRUCTION_CODES_MIPS_H_ 5 #ifndef V8_COMPILER_MIPS_INSTRUCTION_CODES_MIPS_H_
6 #define V8_COMPILER_MIPS_INSTRUCTION_CODES_MIPS_H_ 6 #define V8_COMPILER_MIPS_INSTRUCTION_CODES_MIPS_H_
7 7
8 namespace v8 { 8 namespace v8 {
9 namespace internal { 9 namespace internal {
10 namespace compiler { 10 namespace compiler {
(...skipping 50 matching lines...) Expand 10 before | Expand all | Expand 10 after
61 V(MipsFloat32RoundTruncate) \ 61 V(MipsFloat32RoundTruncate) \
62 V(MipsFloat32RoundUp) \ 62 V(MipsFloat32RoundUp) \
63 V(MipsFloat32RoundTiesEven) \ 63 V(MipsFloat32RoundTiesEven) \
64 V(MipsFloat64RoundDown) \ 64 V(MipsFloat64RoundDown) \
65 V(MipsFloat64RoundTruncate) \ 65 V(MipsFloat64RoundTruncate) \
66 V(MipsFloat64RoundUp) \ 66 V(MipsFloat64RoundUp) \
67 V(MipsFloat64RoundTiesEven) \ 67 V(MipsFloat64RoundTiesEven) \
68 V(MipsCvtSD) \ 68 V(MipsCvtSD) \
69 V(MipsCvtDS) \ 69 V(MipsCvtDS) \
70 V(MipsTruncWD) \ 70 V(MipsTruncWD) \
71 V(MipsRoundWD) \
72 V(MipsFloorWD) \
73 V(MipsCeilWD) \
71 V(MipsTruncUwD) \ 74 V(MipsTruncUwD) \
72 V(MipsCvtDW) \ 75 V(MipsCvtDW) \
73 V(MipsCvtDUw) \ 76 V(MipsCvtDUw) \
74 V(MipsLb) \ 77 V(MipsLb) \
75 V(MipsLbu) \ 78 V(MipsLbu) \
76 V(MipsSb) \ 79 V(MipsSb) \
77 V(MipsLh) \ 80 V(MipsLh) \
78 V(MipsLhu) \ 81 V(MipsLhu) \
79 V(MipsSh) \ 82 V(MipsSh) \
80 V(MipsLw) \ 83 V(MipsLw) \
(...skipping 32 matching lines...) Expand 10 before | Expand all | Expand 10 after
113 #define TARGET_ADDRESSING_MODE_LIST(V) \ 116 #define TARGET_ADDRESSING_MODE_LIST(V) \
114 V(MRI) /* [%r0 + K] */ \ 117 V(MRI) /* [%r0 + K] */ \
115 V(MRR) /* [%r0 + %r1] */ 118 V(MRR) /* [%r0 + %r1] */
116 119
117 120
118 } // namespace compiler 121 } // namespace compiler
119 } // namespace internal 122 } // namespace internal
120 } // namespace v8 123 } // namespace v8
121 124
122 #endif // V8_COMPILER_MIPS_INSTRUCTION_CODES_MIPS_H_ 125 #endif // V8_COMPILER_MIPS_INSTRUCTION_CODES_MIPS_H_
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