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1 //===- subzero/src/IceAssemblerARM32.cpp - Assembler for ARM32 --*- C++ -*-===// | 1 //===- subzero/src/IceAssemblerARM32.cpp - Assembler for ARM32 --*- C++ -*-===// |
2 // | 2 // |
3 // Copyright (c) 2013, the Dart project authors. Please see the AUTHORS file | 3 // Copyright (c) 2013, the Dart project authors. Please see the AUTHORS file |
4 // for details. All rights reserved. Use of this source code is governed by a | 4 // for details. All rights reserved. Use of this source code is governed by a |
5 // BSD-style license that can be found in the LICENSE file. | 5 // BSD-style license that can be found in the LICENSE file. |
6 // | 6 // |
7 // Modified by the Subzero authors. | 7 // Modified by the Subzero authors. |
8 // | 8 // |
9 //===----------------------------------------------------------------------===// | 9 //===----------------------------------------------------------------------===// |
10 // | 10 // |
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1188 verifyRegNotPc(Rd, "Rd", InstName); | 1188 verifyRegNotPc(Rd, "Rd", InstName); |
1189 verifyRegNotPc(Rm, "Rm", InstName); | 1189 verifyRegNotPc(Rm, "Rm", InstName); |
1190 verifyRegNotPc(Rs, "Rs", InstName); | 1190 verifyRegNotPc(Rs, "Rs", InstName); |
1191 emitType01(Cond, kInstTypeDataRegShift, ShiftOpcode, SetFlags, Rn, Rd, | 1191 emitType01(Cond, kInstTypeDataRegShift, ShiftOpcode, SetFlags, Rn, Rd, |
1192 encodeShiftRotateReg(Rm, Shift, Rs), NoChecks, InstName); | 1192 encodeShiftRotateReg(Rm, Shift, Rs), NoChecks, InstName); |
1193 return; | 1193 return; |
1194 } | 1194 } |
1195 } | 1195 } |
1196 } | 1196 } |
1197 | 1197 |
| 1198 void AssemblerARM32::asr(const Operand *OpRd, const Operand *OpRm, |
| 1199 const Operand *OpSrc1, bool SetFlags, |
| 1200 CondARM32::Cond Cond) { |
| 1201 constexpr const char *AsrName = "asr"; |
| 1202 emitShift(Cond, OperandARM32::ASR, OpRd, OpRm, OpSrc1, SetFlags, AsrName); |
| 1203 } |
| 1204 |
1198 void AssemblerARM32::lsl(const Operand *OpRd, const Operand *OpRm, | 1205 void AssemblerARM32::lsl(const Operand *OpRd, const Operand *OpRm, |
1199 const Operand *OpSrc1, bool SetFlags, | 1206 const Operand *OpSrc1, bool SetFlags, |
1200 CondARM32::Cond Cond) { | 1207 CondARM32::Cond Cond) { |
1201 constexpr const char *LslName = "lsl"; | 1208 constexpr const char *LslName = "lsl"; |
1202 emitShift(Cond, OperandARM32::LSL, OpRd, OpRm, OpSrc1, SetFlags, LslName); | 1209 emitShift(Cond, OperandARM32::LSL, OpRd, OpRm, OpSrc1, SetFlags, LslName); |
1203 } | 1210 } |
1204 | 1211 |
1205 void AssemblerARM32::lsr(const Operand *OpRd, const Operand *OpRm, | 1212 void AssemblerARM32::lsr(const Operand *OpRd, const Operand *OpRm, |
1206 const Operand *OpSrc1, bool SetFlags, | 1213 const Operand *OpSrc1, bool SetFlags, |
1207 CondARM32::Cond Cond) { | 1214 CondARM32::Cond Cond) { |
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1633 | 1640 |
1634 void AssemblerARM32::uxt(const Operand *OpRd, const Operand *OpSrc0, | 1641 void AssemblerARM32::uxt(const Operand *OpRd, const Operand *OpSrc0, |
1635 CondARM32::Cond Cond) { | 1642 CondARM32::Cond Cond) { |
1636 constexpr const char *UxtName = "uxt"; | 1643 constexpr const char *UxtName = "uxt"; |
1637 constexpr IValueT UxtOpcode = B26 | B25 | B23 | B22 | B21; | 1644 constexpr IValueT UxtOpcode = B26 | B25 | B23 | B22 | B21; |
1638 emitSignExtend(Cond, UxtOpcode, OpRd, OpSrc0, UxtName); | 1645 emitSignExtend(Cond, UxtOpcode, OpRd, OpSrc0, UxtName); |
1639 } | 1646 } |
1640 | 1647 |
1641 } // end of namespace ARM32 | 1648 } // end of namespace ARM32 |
1642 } // end of namespace Ice | 1649 } // end of namespace Ice |
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