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| 1 // Copyright (c) 2013, the Dart project authors. Please see the AUTHORS file | 1 // Copyright (c) 2013, the Dart project authors. Please see the AUTHORS file |
| 2 // for details. All rights reserved. Use of this source code is governed by a | 2 // for details. All rights reserved. Use of this source code is governed by a |
| 3 // BSD-style license that can be found in the LICENSE file. | 3 // BSD-style license that can be found in the LICENSE file. |
| 4 // | 4 // |
| 5 // This is forked from Dart revision df52deea9f25690eb8b66c5995da92b70f7ac1fe | 5 // This is forked from Dart revision df52deea9f25690eb8b66c5995da92b70f7ac1fe |
| 6 // Please update the (git) revision if we merge changes from Dart. | 6 // Please update the (git) revision if we merge changes from Dart. |
| 7 // https://code.google.com/p/dart/wiki/GettingTheSource | 7 // https://code.google.com/p/dart/wiki/GettingTheSource |
| 8 | 8 |
| 9 #include "vm/globals.h" // NOLINT | 9 #include "vm/globals.h" // NOLINT |
| 10 #if defined(TARGET_ARCH_ARM) | 10 #if defined(TARGET_ARCH_ARM) |
| (...skipping 2602 matching lines...) Expand 10 before | Expand all | Expand 10 after Loading... |
| 2613 if (shift == 32) { | 2613 if (shift == 32) { |
| 2614 shift = 0; // Comply to UAL syntax. | 2614 shift = 0; // Comply to UAL syntax. |
| 2615 } | 2615 } |
| 2616 mov(rd, Operand(rm, LSR, shift), cond); | 2616 mov(rd, Operand(rm, LSR, shift), cond); |
| 2617 } | 2617 } |
| 2618 | 2618 |
| 2619 // Moved to ARM32::AssemblerARM32::lsr() | 2619 // Moved to ARM32::AssemblerARM32::lsr() |
| 2620 void Assembler::Lsr(Register rd, Register rm, Register rs, Condition cond) { | 2620 void Assembler::Lsr(Register rd, Register rm, Register rs, Condition cond) { |
| 2621 mov(rd, Operand(rm, LSR, rs), cond); | 2621 mov(rd, Operand(rm, LSR, rs), cond); |
| 2622 } | 2622 } |
| 2623 #endif | |
| 2624 | 2623 |
| 2625 | 2624 // Moved to ARM32::AssemblerARM32::asr() |
| 2626 void Assembler::Asr(Register rd, Register rm, const Operand& shift_imm, | 2625 void Assembler::Asr(Register rd, Register rm, const Operand& shift_imm, |
| 2627 Condition cond) { | 2626 Condition cond) { |
| 2628 ASSERT(shift_imm.type() == 1); | 2627 ASSERT(shift_imm.type() == 1); |
| 2629 uint32_t shift = shift_imm.encoding(); | 2628 uint32_t shift = shift_imm.encoding(); |
| 2630 ASSERT(shift != 0); // Do not use Asr if no shift is wanted. | 2629 ASSERT(shift != 0); // Do not use Asr if no shift is wanted. |
| 2631 if (shift == 32) { | 2630 if (shift == 32) { |
| 2632 shift = 0; // Comply to UAL syntax. | 2631 shift = 0; // Comply to UAL syntax. |
| 2633 } | 2632 } |
| 2634 mov(rd, Operand(rm, ASR, shift), cond); | 2633 mov(rd, Operand(rm, ASR, shift), cond); |
| 2635 } | 2634 } |
| 2636 | 2635 #endif |
| 2637 | 2636 |
| 2638 void Assembler::Asrs(Register rd, Register rm, const Operand& shift_imm, | 2637 void Assembler::Asrs(Register rd, Register rm, const Operand& shift_imm, |
| 2639 Condition cond) { | 2638 Condition cond) { |
| 2640 ASSERT(shift_imm.type() == 1); | 2639 ASSERT(shift_imm.type() == 1); |
| 2641 uint32_t shift = shift_imm.encoding(); | 2640 uint32_t shift = shift_imm.encoding(); |
| 2642 ASSERT(shift != 0); // Do not use Asr if no shift is wanted. | 2641 ASSERT(shift != 0); // Do not use Asr if no shift is wanted. |
| 2643 if (shift == 32) { | 2642 if (shift == 32) { |
| 2644 shift = 0; // Comply to UAL syntax. | 2643 shift = 0; // Comply to UAL syntax. |
| 2645 } | 2644 } |
| 2646 movs(rd, Operand(rm, ASR, shift), cond); | 2645 movs(rd, Operand(rm, ASR, shift), cond); |
| 2647 } | 2646 } |
| 2648 | 2647 |
| 2649 | 2648 #if 0 |
| 2649 // Moved to ARM32::AssemblerARM32::asr() |
| 2650 void Assembler::Asr(Register rd, Register rm, Register rs, Condition cond) { | 2650 void Assembler::Asr(Register rd, Register rm, Register rs, Condition cond) { |
| 2651 mov(rd, Operand(rm, ASR, rs), cond); | 2651 mov(rd, Operand(rm, ASR, rs), cond); |
| 2652 } | 2652 } |
| 2653 | 2653 #endif |
| 2654 | 2654 |
| 2655 void Assembler::Ror(Register rd, Register rm, const Operand& shift_imm, | 2655 void Assembler::Ror(Register rd, Register rm, const Operand& shift_imm, |
| 2656 Condition cond) { | 2656 Condition cond) { |
| 2657 ASSERT(shift_imm.type() == 1); | 2657 ASSERT(shift_imm.type() == 1); |
| 2658 ASSERT(shift_imm.encoding() != 0); // Use Rrx instruction. | 2658 ASSERT(shift_imm.encoding() != 0); // Use Rrx instruction. |
| 2659 mov(rd, Operand(rm, ROR, shift_imm.encoding()), cond); | 2659 mov(rd, Operand(rm, ROR, shift_imm.encoding()), cond); |
| 2660 } | 2660 } |
| 2661 | 2661 |
| 2662 | 2662 |
| 2663 void Assembler::Ror(Register rd, Register rm, Register rs, Condition cond) { | 2663 void Assembler::Ror(Register rd, Register rm, Register rs, Condition cond) { |
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| 3687 | 3687 |
| 3688 | 3688 |
| 3689 const char* Assembler::FpuRegisterName(FpuRegister reg) { | 3689 const char* Assembler::FpuRegisterName(FpuRegister reg) { |
| 3690 ASSERT((0 <= reg) && (reg < kNumberOfFpuRegisters)); | 3690 ASSERT((0 <= reg) && (reg < kNumberOfFpuRegisters)); |
| 3691 return fpu_reg_names[reg]; | 3691 return fpu_reg_names[reg]; |
| 3692 } | 3692 } |
| 3693 | 3693 |
| 3694 } // namespace dart | 3694 } // namespace dart |
| 3695 | 3695 |
| 3696 #endif // defined TARGET_ARCH_ARM | 3696 #endif // defined TARGET_ARCH_ARM |
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