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Issue 1508423003: Subzero. ARM32. Introduces explicit register parameter attribute. (Closed) Base URL: https://chromium.googlesource.com/native_client/pnacl-subzero.git@master
Patch Set: New IceRegistersARM32.def file. Created 5 years ago
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1 //===- subzero/src/IceInstARM32.def - X-Macros for ARM32 insts --*- C++ -*-===// 1 //===- subzero/src/IceInstARM32.def - X-Macros for ARM32 insts --*- C++ -*-===//
2 // 2 //
3 // The Subzero Code Generator 3 // The Subzero Code Generator
4 // 4 //
5 // This file is distributed under the University of Illinois Open Source 5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details. 6 // License. See LICENSE.TXT for details.
7 // 7 //
8 //===----------------------------------------------------------------------===// 8 //===----------------------------------------------------------------------===//
9 // 9 //
10 // This file defines properties of ARM32 instructions in the form of x-macros. 10 // This file defines properties of ARM32 instructions in the form of x-macros.
(...skipping 14 matching lines...) Expand all
25 // IP is not considered isInt to reserve it as a scratch register. A scratch 25 // IP is not considered isInt to reserve it as a scratch register. A scratch
26 // register is useful for expanding instructions post-register allocation. 26 // register is useful for expanding instructions post-register allocation.
27 // 27 //
28 // LR is not considered isInt to avoid being allocated as a register. It is 28 // LR is not considered isInt to avoid being allocated as a register. It is
29 // technically preserved, but save/restore is handled separately, based on 29 // technically preserved, but save/restore is handled separately, based on
30 // whether or not the function MaybeLeafFunc. 30 // whether or not the function MaybeLeafFunc.
31 // 31 //
32 // The register tables can be generated using the gen_arm32_reg_tables.py 32 // The register tables can be generated using the gen_arm32_reg_tables.py
33 // script. 33 // script.
34 34
35 #define REGARM32_GPR_TABLE \ 35 #include "IceRegistersARM32.def"
36 /* val, encode, name, scratch,preserved,stackptr,frameptr, \ 36 // The register tables defined in IceRegistersARM32 use the following x-macro:
37 isInt,isI64Pair,isFP32,isFP64,isVec128, alias_init */ \ 37 //#define X(val, encode, name, cc_arg, scratch, preserved, stackptr, frameptr,
38 X(Reg_r0, 0, "r0", 1,0,0,0, 1,0,0,0,0, REGLIST1(RegARM32, r0r1)) \
39 X(Reg_r1, 1, "r1", 1,0,0,0, 1,0,0,0,0, REGLIST1(RegARM32, r0r1)) \
40 X(Reg_r2, 2, "r2", 1,0,0,0, 1,0,0,0,0, REGLIST1(RegARM32, r2r3)) \
41 X(Reg_r3, 3, "r3", 1,0,0,0, 1,0,0,0,0, REGLIST1(RegARM32, r2r3)) \
42 X(Reg_r4, 4, "r4", 0,1,0,0, 1,0,0,0,0, REGLIST1(RegARM32, r4r5)) \
43 X(Reg_r5, 5, "r5", 0,1,0,0, 1,0,0,0,0, REGLIST1(RegARM32, r4r5)) \
44 X(Reg_r6, 6, "r6", 0,1,0,0, 1,0,0,0,0, REGLIST1(RegARM32, r6r7)) \
45 X(Reg_r7, 7, "r7", 0,1,0,0, 1,0,0,0,0, REGLIST1(RegARM32, r6r7)) \
46 X(Reg_r8, 8, "r8", 0,1,0,0, 1,0,0,0,0, REGLIST1(RegARM32, r8r9)) \
47 X(Reg_r9, 9, "r9", 0,1,0,0, 0,0,0,0,0, REGLIST1(RegARM32, r8r9)) \
48 X(Reg_r10, 10, "r10", 0,1,0,0, 1,0,0,0,0, REGLIST1(RegARM32, r10fp)) \
49 X(Reg_fp, 11, "fp", 0,1,0,1, 1,0,0,0,0, REGLIST1(RegARM32, r10fp)) \
50 X(Reg_ip, 12, "ip", 1,0,0,0, 0,0,0,0,0, REGLIST1(RegARM32, ip)) \
51 X(Reg_sp, 13, "sp", 0,0,1,0, 0,0,0,0,0, REGLIST1(RegARM32, sp)) \
52 X(Reg_lr, 14, "lr", 0,0,0,0, 0,0,0,0,0, REGLIST1(RegARM32, lr)) \
53 X(Reg_pc, 15, "pc", 0,0,0,0, 0,0,0,0,0, REGLIST1(RegARM32, pc))
54 //#define X(val, encode, name, scratch, preserved, stackptr, frameptr,
55 // isInt, isI64Pair, isFP32, isFP64, isVec128, alias_init)
56
57 // The following defines a table with the available pairs of consecutive i32
58 // GPRs starting at an even GPR that is not r14. Those are used to hold i64
59 // variables for atomic memory operations. If one of the registers in the pair
60 // is preserved, then we mark the whole pair as preserved to help the register
61 // allocator.
62 #define REGARM32_I64PAIR_TABLE \
63 /* val, encode, name, scratch,preserved,stackptr,frameptr, \
64 isInt,isI64Pair,isFP32,isFP64,isVec128, alias_init */ \
65 X(Reg_r0r1, 0, "r0, r1", 1,0,0,0, 0,1,0,0,0, REGLIST2(RegARM32, r0, r1)) \
66 X(Reg_r2r3, 2, "r2, r3", 1,0,0,0, 0,1,0,0,0, REGLIST2(RegARM32, r2, r3)) \
67 X(Reg_r4r5, 4, "r4, r5", 0,1,0,0, 0,1,0,0,0, REGLIST2(RegARM32, r4, r5)) \
68 X(Reg_r6r7, 6, "r6, r7", 0,1,0,0, 0,1,0,0,0, REGLIST2(RegARM32, r6, r7)) \
69 X(Reg_r8r9, 8, "r8, r9", 0,1,0,0, 0,0,0,0,0, REGLIST2(RegARM32, r8, r9)) \
70 X(Reg_r10fp, 10, "r10, fp", 0,1,0,0, 0,0,0,0,0, REGLIST2(RegARM32, r10, fp))
71 //#define X(val, encode, name, scratch, preserved, stackptr, frameptr,
72 // isInt, isI64Pair, isFP32, isFP64, isVec128, alias_init)
73
74 // S registers 0-15 are scratch, but 16-31 are preserved.
75 #define REGARM32_FP32_TABLE \
76 /* val, encode, name, scratch,preserved,stackptr,frameptr, \
77 isInt,isI64Pair,isFP32,isFP64,isVec128, alias_init */ \
78 X(Reg_s0, 0, "s0", 1,0,0,0, 0,0,1,0,0, REGLIST2(RegARM32, d0, q0)) \
79 X(Reg_s1, 1, "s1", 1,0,0,0, 0,0,1,0,0, REGLIST2(RegARM32, d0, q0)) \
80 X(Reg_s2, 2, "s2", 1,0,0,0, 0,0,1,0,0, REGLIST2(RegARM32, d1, q0)) \
81 X(Reg_s3, 3, "s3", 1,0,0,0, 0,0,1,0,0, REGLIST2(RegARM32, d1, q0)) \
82 X(Reg_s4, 4, "s4", 1,0,0,0, 0,0,1,0,0, REGLIST2(RegARM32, d2, q1)) \
83 X(Reg_s5, 5, "s5", 1,0,0,0, 0,0,1,0,0, REGLIST2(RegARM32, d2, q1)) \
84 X(Reg_s6, 6, "s6", 1,0,0,0, 0,0,1,0,0, REGLIST2(RegARM32, d3, q1)) \
85 X(Reg_s7, 7, "s7", 1,0,0,0, 0,0,1,0,0, REGLIST2(RegARM32, d3, q1)) \
86 X(Reg_s8, 8, "s8", 1,0,0,0, 0,0,1,0,0, REGLIST2(RegARM32, d4, q2)) \
87 X(Reg_s9, 9, "s9", 1,0,0,0, 0,0,1,0,0, REGLIST2(RegARM32, d4, q2)) \
88 X(Reg_s10, 10, "s10", 1,0,0,0, 0,0,1,0,0, REGLIST2(RegARM32, d5, q2)) \
89 X(Reg_s11, 11, "s11", 1,0,0,0, 0,0,1,0,0, REGLIST2(RegARM32, d5, q2)) \
90 X(Reg_s12, 12, "s12", 1,0,0,0, 0,0,1,0,0, REGLIST2(RegARM32, d6, q3)) \
91 X(Reg_s13, 13, "s13", 1,0,0,0, 0,0,1,0,0, REGLIST2(RegARM32, d6, q3)) \
92 X(Reg_s14, 14, "s14", 1,0,0,0, 0,0,1,0,0, REGLIST2(RegARM32, d7, q3)) \
93 X(Reg_s15, 15, "s15", 1,0,0,0, 0,0,1,0,0, REGLIST2(RegARM32, d7, q3)) \
94 X(Reg_s16, 16, "s16", 0,1,0,0, 0,0,1,0,0, REGLIST2(RegARM32, d8, q4)) \
95 X(Reg_s17, 17, "s17", 0,1,0,0, 0,0,1,0,0, REGLIST2(RegARM32, d8, q4)) \
96 X(Reg_s18, 18, "s18", 0,1,0,0, 0,0,1,0,0, REGLIST2(RegARM32, d9, q4)) \
97 X(Reg_s19, 19, "s19", 0,1,0,0, 0,0,1,0,0, REGLIST2(RegARM32, d9, q4)) \
98 X(Reg_s20, 20, "s20", 0,1,0,0, 0,0,1,0,0, REGLIST2(RegARM32, d10, q5)) \
99 X(Reg_s21, 21, "s21", 0,1,0,0, 0,0,1,0,0, REGLIST2(RegARM32, d10, q5)) \
100 X(Reg_s22, 22, "s22", 0,1,0,0, 0,0,1,0,0, REGLIST2(RegARM32, d11, q5)) \
101 X(Reg_s23, 23, "s23", 0,1,0,0, 0,0,1,0,0, REGLIST2(RegARM32, d11, q5)) \
102 X(Reg_s24, 24, "s24", 0,1,0,0, 0,0,1,0,0, REGLIST2(RegARM32, d12, q6)) \
103 X(Reg_s25, 25, "s25", 0,1,0,0, 0,0,1,0,0, REGLIST2(RegARM32, d12, q6)) \
104 X(Reg_s26, 26, "s26", 0,1,0,0, 0,0,1,0,0, REGLIST2(RegARM32, d13, q6)) \
105 X(Reg_s27, 27, "s27", 0,1,0,0, 0,0,1,0,0, REGLIST2(RegARM32, d13, q6)) \
106 X(Reg_s28, 28, "s28", 0,1,0,0, 0,0,1,0,0, REGLIST2(RegARM32, d14, q7)) \
107 X(Reg_s29, 29, "s29", 0,1,0,0, 0,0,1,0,0, REGLIST2(RegARM32, d14, q7)) \
108 X(Reg_s30, 30, "s30", 0,1,0,0, 0,0,1,0,0, REGLIST2(RegARM32, d15, q7)) \
109 X(Reg_s31, 31, "s31", 0,1,0,0, 0,0,1,0,0, REGLIST2(RegARM32, d15, q7))
110 //#define X(val, encode, name, scratch, preserved, stackptr, frameptr,
111 // isInt, isI64Pair, isFP32,isFP64, isVec128, alias_init)
112
113 // D registers 0-7 are scratch, 8-15 are preserved, and 16-31 are also scratch
114 // (if supported by the D32 feature vs D16). D registers are defined in reverse
115 // order so that, during register allocation, Subzero will prefer higher D
116 // registers. In processors supporting the D32 feature this will effectively
117 // cause double allocation to bias towards allocating "high" D registers, which
118 // do not alias any S registers.
119 #define REGARM32_FP64_TABLE \
120 /* val, encode, name, scratch,preserved,stackptr,frameptr, \
121 isInt,isI64Pair,isFP32,isFP64,isVec128, alias_init */ \
122 X(Reg_d31, 31, "d31", 1,0,0,0, 0,0,0,1,0, REGLIST1(RegARM32, q15)) \
123 X(Reg_d30, 30, "d30", 1,0,0,0, 0,0,0,1,0, REGLIST1(RegARM32, q15)) \
124 X(Reg_d29, 29, "d29", 1,0,0,0, 0,0,0,1,0, REGLIST1(RegARM32, q14)) \
125 X(Reg_d28, 28, "d28", 1,0,0,0, 0,0,0,1,0, REGLIST1(RegARM32, q14)) \
126 X(Reg_d27, 27, "d27", 1,0,0,0, 0,0,0,1,0, REGLIST1(RegARM32, q13)) \
127 X(Reg_d26, 26, "d26", 1,0,0,0, 0,0,0,1,0, REGLIST1(RegARM32, q13)) \
128 X(Reg_d25, 25, "d25", 1,0,0,0, 0,0,0,1,0, REGLIST1(RegARM32, q12)) \
129 X(Reg_d24, 24, "d24", 1,0,0,0, 0,0,0,1,0, REGLIST1(RegARM32, q12)) \
130 X(Reg_d23, 23, "d23", 1,0,0,0, 0,0,0,1,0, REGLIST1(RegARM32, q11)) \
131 X(Reg_d22, 22, "d22", 1,0,0,0, 0,0,0,1,0, REGLIST1(RegARM32, q11)) \
132 X(Reg_d21, 21, "d21", 1,0,0,0, 0,0,0,1,0, REGLIST1(RegARM32, q10)) \
133 X(Reg_d20, 20, "d20", 1,0,0,0, 0,0,0,1,0, REGLIST1(RegARM32, q10)) \
134 X(Reg_d19, 19, "d19", 1,0,0,0, 0,0,0,1,0, REGLIST1(RegARM32, q9)) \
135 X(Reg_d18, 18, "d18", 1,0,0,0, 0,0,0,1,0, REGLIST1(RegARM32, q9)) \
136 X(Reg_d17, 17, "d17", 1,0,0,0, 0,0,0,1,0, REGLIST1(RegARM32, q8)) \
137 X(Reg_d16, 16, "d16", 1,0,0,0, 0,0,0,1,0, REGLIST1(RegARM32, q8)) \
138 X(Reg_d15, 15, "d15", 0,1,0,0, 0,0,0,1,0, REGLIST3(RegARM32, s30, s31, q7)) \
139 X(Reg_d14, 14, "d14", 0,1,0,0, 0,0,0,1,0, REGLIST3(RegARM32, s28, s29, q7)) \
140 X(Reg_d13, 13, "d13", 0,1,0,0, 0,0,0,1,0, REGLIST3(RegARM32, s26, s27, q6)) \
141 X(Reg_d12, 12, "d12", 0,1,0,0, 0,0,0,1,0, REGLIST3(RegARM32, s24, s25, q6)) \
142 X(Reg_d11, 11, "d11", 0,1,0,0, 0,0,0,1,0, REGLIST3(RegARM32, s22, s23, q5)) \
143 X(Reg_d10, 10, "d10", 0,1,0,0, 0,0,0,1,0, REGLIST3(RegARM32, s20, s21, q5)) \
144 X(Reg_d9, 9, "d9", 0,1,0,0, 0,0,0,1,0, REGLIST3(RegARM32, s18, s19, q4)) \
145 X(Reg_d8, 8, "d8", 0,1,0,0, 0,0,0,1,0, REGLIST3(RegARM32, s16, s17, q4)) \
146 X(Reg_d7, 7, "d7", 1,0,0,0, 0,0,0,1,0, REGLIST3(RegARM32, s14, s15, q3)) \
147 X(Reg_d6, 6, "d6", 1,0,0,0, 0,0,0,1,0, REGLIST3(RegARM32, s12, s13, q3)) \
148 X(Reg_d5, 5, "d5", 1,0,0,0, 0,0,0,1,0, REGLIST3(RegARM32, s10, s11, q2)) \
149 X(Reg_d4, 4, "d4", 1,0,0,0, 0,0,0,1,0, REGLIST3(RegARM32, s8, s9, q2)) \
150 X(Reg_d3, 3, "d3", 1,0,0,0, 0,0,0,1,0, REGLIST3(RegARM32, s6, s7, q1)) \
151 X(Reg_d2, 2, "d2", 1,0,0,0, 0,0,0,1,0, REGLIST3(RegARM32, s4, s5, q1)) \
152 X(Reg_d1, 1, "d1", 1,0,0,0, 0,0,0,1,0, REGLIST3(RegARM32, s2, s3, q0)) \
153 X(Reg_d0, 0, "d0", 1,0,0,0, 0,0,0,1,0, REGLIST3(RegARM32, s0, s1, q0))
154 //#define X(val, encode, name, scratch, preserved, stackptr, frameptr,
155 // isInt, isI64Pair, isFP32, isFP64, isVec128, alias_init)
156
157 // Q registers 0-3 are scratch, 4-7 are preserved, and 8-15 are also scratch
158 // (if supported by the D32 feature). Q registers are defined in reverse order
159 // for the same reason as D registers.
160 #define REGARM32_VEC128_TABLE \
161 /* val, encode, name, scratch, preserved, stackptr, frameptr, \
162 isInt, isI64Pair, isFP32, isFP64, isVec128, alias_init */ \
163 X(Reg_q15, 15, "q15", 1, 0, 0, 0, 0, 0, 0, 0, 1, \
164 REGLIST2(RegARM32, d30, d31)) \
165 X(Reg_q14, 14, "q14", 1, 0, 0, 0, 0, 0, 0, 0, 1, \
166 REGLIST2(RegARM32, d28, d29)) \
167 X(Reg_q13, 13, "q13", 1, 0, 0, 0, 0, 0, 0, 0, 1, \
168 REGLIST2(RegARM32, d26, d27)) \
169 X(Reg_q12, 12, "q12", 1, 0, 0, 0, 0, 0, 0, 0, 1, \
170 REGLIST2(RegARM32, d24, d25)) \
171 X(Reg_q11, 11, "q11", 1, 0, 0, 0, 0, 0, 0, 0, 1, \
172 REGLIST2(RegARM32, d22, d23)) \
173 X(Reg_q10, 10, "q10", 1, 0, 0, 0, 0, 0, 0, 0, 1, \
174 REGLIST2(RegARM32, d20, d21)) \
175 X(Reg_q9, 9, "q9", 1, 0, 0, 0, 0, 0, 0, 0, 1, \
176 REGLIST2(RegARM32, d18, d19)) \
177 X(Reg_q8, 8, "q8", 1, 0, 0, 0, 0, 0, 0, 0, 1, \
178 REGLIST2(RegARM32, d16, d17)) \
179 X(Reg_q7, 7, "q7", 0, 1, 0, 0, 0, 0, 0, 0, 1, \
180 REGLIST6(RegARM32, s28, s29, s30, s31, d14, d15)) \
181 X(Reg_q6, 6, "q6", 0, 1, 0, 0, 0, 0, 0, 0, 1, \
182 REGLIST6(RegARM32, s24, s25, s26, s27, d12, d13)) \
183 X(Reg_q5, 5, "q5", 0, 1, 0, 0, 0, 0, 0, 0, 1, \
184 REGLIST6(RegARM32, s20, s21, s22, s23, d10, d11)) \
185 X(Reg_q4, 4, "q4", 0, 1, 0, 0, 0, 0, 0, 0, 1, \
186 REGLIST6(RegARM32, s16, s17, s18, s19, d8, d9)) \
187 X(Reg_q3, 3, "q3", 1, 0, 0, 0, 0, 0, 0, 0, 1, \
188 REGLIST6(RegARM32, s12, s13, s14, s15, d6, d7)) \
189 X(Reg_q2, 2, "q2", 1, 0, 0, 0, 0, 0, 0, 0, 1, \
190 REGLIST6(RegARM32, s8, s9, s10, s11, d4, d5)) \
191 X(Reg_q1, 1, "q1", 1, 0, 0, 0, 0, 0, 0, 0, 1, \
192 REGLIST6(RegARM32, s4, s5, s6, s7, d2, d3)) \
193 X(Reg_q0, 0, "q0", 1, 0, 0, 0, 0, 0, 0, 0, 1, \
194 REGLIST6(RegARM32, s0, s1, s2, s3, d0, d1))
195 //#define X(val, encode, name, scratch, preserved, stackptr, frameptr,
196 // isInt, isI64Pair, isFP32, isFP64, isVec128, alias_init) 38 // isInt, isI64Pair, isFP32, isFP64, isVec128, alias_init)
197 39
198 // We also provide a combined table, so that there is a namespace where all of 40 // We also provide a combined table, so that there is a namespace where all of
199 // the registers are considered and have distinct numberings. This is in 41 // the registers are considered and have distinct numberings. This is in
200 // contrast to the above, where the "encode" is based on how the register 42 // contrast to the above, where the "encode" is based on how the register
201 // numbers will be encoded in binaries and values can overlap. 43 // numbers will be encoded in binaries and values can overlap.
202 #define REGARM32_TABLE \ 44 #define REGARM32_TABLE \
203 /* val, encode, name, scratch, preserved, stackptr, frameptr, isInt, \ 45 /* val, encode, name, cc_arg, scratch, preserved, stackptr, frameptr, \
204 isFP32, isFP64, isVec128, alias_init */ \ 46 isInt, isI64Pair, isFP32, isFP64, isVec128, alias_init */ \
205 REGARM32_GPR_TABLE \ 47 REGARM32_GPR_TABLE \
206 REGARM32_I64PAIR_TABLE \ 48 REGARM32_I64PAIR_TABLE \
207 REGARM32_FP32_TABLE \ 49 REGARM32_FP32_TABLE \
208 REGARM32_FP64_TABLE \ 50 REGARM32_FP64_TABLE \
209 REGARM32_VEC128_TABLE 51 REGARM32_VEC128_TABLE
210 //#define X(val, encode, name, scratch, preserved, stackptr, frameptr, 52 //#define X(val, encode, name, cc_arg, scratch, preserved, stackptr, frameptr,
211 // isInt, isFP32, isFP64, isVec128, alias_init) 53 // isInt, isFP32, isFP64, isVec128, alias_init)
212 54
213 #define REGARM32_TABLE_BOUNDS \ 55 #define REGARM32_TABLE_BOUNDS \
214 /* val, init */ \ 56 /* val, init */ \
215 X(Reg_GPR_First, = Reg_r0) \ 57 X(Reg_GPR_First, = Reg_r0) \
216 X(Reg_GPR_Last, = Reg_pc) \ 58 X(Reg_GPR_Last, = Reg_pc) \
217 X(Reg_I64PAIR_First, = Reg_r0r1) \ 59 X(Reg_I64PAIR_First, = Reg_r0r1) \
218 X(Reg_I64PAIR_Last, = Reg_r10fp) \ 60 X(Reg_I64PAIR_Last, = Reg_r10fp) \
219 X(Reg_SREG_First, = Reg_s0) \ 61 X(Reg_SREG_First, = Reg_s0) \
220 X(Reg_SREG_Last, = Reg_s31) \ 62 X(Reg_SREG_Last, = Reg_s31) \
(...skipping 53 matching lines...) Expand 10 before | Expand all | Expand 10 after
274 X(LS, 9, HI, "ls") /* unsigned lower or same */ \ 116 X(LS, 9, HI, "ls") /* unsigned lower or same */ \
275 X(GE, 10, LT, "ge") /* signed greater than or equal */ \ 117 X(GE, 10, LT, "ge") /* signed greater than or equal */ \
276 X(LT, 11, GE, "lt") /* signed less than */ \ 118 X(LT, 11, GE, "lt") /* signed less than */ \
277 X(GT, 12, LE, "gt") /* signed greater than */ \ 119 X(GT, 12, LE, "gt") /* signed greater than */ \
278 X(LE, 13, GT, "le") /* signed less than or equal */ \ 120 X(LE, 13, GT, "le") /* signed less than or equal */ \
279 X(AL, 14, kNone, "") /* always (unconditional) */ \ 121 X(AL, 14, kNone, "") /* always (unconditional) */ \
280 X(kNone, 15, kNone, "??") /* special condition / none */ 122 X(kNone, 15, kNone, "??") /* special condition / none */
281 //#define X(tag, encode, opp, emit) 123 //#define X(tag, encode, opp, emit)
282 124
283 #endif // SUBZERO_SRC_ICEINSTARM32_DEF 125 #endif // SUBZERO_SRC_ICEINSTARM32_DEF
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