Chromium Code Reviews Chromium Code Reviews
Issue 1508423003:
Subzero. ARM32. Introduces explicit register parameter attribute. (Closed)
Base URL: https://chromium.googlesource.com/native_client/pnacl-subzero.git@master| OLD | NEW |
|---|---|
| 1 class RegAliases(object): | 1 class RegAliases(object): |
| 2 def __init__(self, *Aliases): | 2 def __init__(self, AliasesStr): |
| 3 self.Aliases = list(Aliases) | 3 self.Aliases = list(Alias.strip() for Alias in AliasesStr.split(',')) |
| 4 | 4 |
| 5 def __str__(self): | 5 def __str__(self): |
| 6 return 'REGLIST{AliasCount}(RegARM32, {Aliases})'.format( | 6 return 'REGLIST{AliasCount}(RegARM32, {Aliases})'.format( |
| 7 AliasCount=len(self.Aliases), Aliases=', '.join(self.Aliases)) | 7 AliasCount=len(self.Aliases), Aliases=', '.join(self.Aliases)) |
| 8 | 8 |
| 9 def _ArgumentNames(Method): | 9 def _ArgumentNames(Method): |
| 10 import inspect | 10 import inspect |
| 11 return (ArgName for ArgName in inspect.getargspec(Method).args | 11 return (ArgName for ArgName in inspect.getargspec(Method).args |
| 12 if ArgName != 'self') | 12 if ArgName != 'self') |
| 13 | 13 |
| 14 class RegFeatures(object): | 14 class RegFeatures(object): |
| 15 def __init__(self, IsScratch=0, IsPreserved=0, IsStackPtr=0, IsFramePtr=0, | 15 def __init__(self, AsmStr=None, CCArg=0, IsScratch=0, IsPreserved=0, |
| 16 IsInt=0, IsI64Pair=0, IsFP32=0, IsFP64=0, IsVec128=0, | 16 IsStackPtr=0, IsFramePtr=0, IsInt=0, IsI64Pair=0, IsFP32=0, |
| 17 Aliases=None): | 17 IsFP64=0, IsVec128=0, Aliases=None): |
| 18 assert not (IsInt and IsI64Pair) | 18 assert not (IsInt and IsI64Pair) |
| 19 assert not (IsFP32 and IsFP64) | 19 assert not (IsFP32 and IsFP64) |
| 20 assert not (IsFP32 and IsVec128) | 20 assert not (IsFP32 and IsVec128) |
| 21 assert not (IsFP64 and IsVec128) | 21 assert not (IsFP64 and IsVec128) |
| 22 assert not ((IsInt or IsI64Pair) and (IsFP32 or IsFP64 or IsVec128)) | 22 assert not ((IsInt or IsI64Pair) and (IsFP32 or IsFP64 or IsVec128)) |
| 23 assert (not IsFramePtr) or IsInt | 23 assert (not IsFramePtr) or IsInt |
| 24 assert (not IsStackPtr) or not( | 24 assert (not IsStackPtr) or not( |
| 25 IsInt or IsI64Pair or IsFP32 or IsFP64 or IsVec128) | 25 IsInt or IsI64Pair or IsFP32 or IsFP64 or IsVec128) |
| 26 assert not (IsScratch and IsPreserved) | 26 assert not (IsScratch and IsPreserved) |
| 27 self.Features = [x for x in _ArgumentNames(self.__init__)] | 27 self.Features = [x for x in _ArgumentNames(self.__init__)] |
| 28 self.FeaturesDict = {} | 28 self.FeaturesDict = {} |
| 29 # The argument Aliases is a string with the register aliasing information. | |
| 30 # The next line convert it to a RegAlias object, for pretty printing. | |
| 31 Aliases = RegAliases(Aliases) | |
| 32 AsmStr = '"%s"' % AsmStr | |
| 29 for Feature in self.Features: | 33 for Feature in self.Features: |
| 30 self.FeaturesDict[Feature] = locals()[Feature] | 34 self.FeaturesDict[Feature] = locals()[Feature] |
| 31 | 35 |
| 32 def __str__(self): | 36 def __str__(self): |
| 33 return '%s' % (', '.join(str(self.FeaturesDict[Feature]) for | 37 return '%s' % (', '.join(str(self.FeaturesDict[Feature]) for |
| 34 Feature in self.Features)) | 38 Feature in self.Features)) |
| 35 | 39 |
| 36 def Aliases(self): | 40 def Aliases(self): |
| 37 return self.FeaturesDict['Aliases'] | 41 return self.FeaturesDict['Aliases'] |
| 38 | 42 |
| 39 def LivesInGPR(self): | 43 def LivesInGPR(self): |
| 40 return (any(self.FeaturesDict[IntFeature] for IntFeature in ( | 44 return (any(self.FeaturesDict[IntFeature] for IntFeature in ( |
| 41 'IsInt', 'IsI64Pair', 'IsStackPtr', 'IsFramePtr')) or | 45 'IsInt', 'IsI64Pair', 'IsStackPtr', 'IsFramePtr')) or |
| 42 not self.LivesInVFP()) | 46 not self.LivesInVFP()) |
| 43 | 47 |
| 44 def LivesInVFP(self): | 48 def LivesInVFP(self): |
| 45 return any(self.FeaturesDict[FpFeature] for FpFeature in ( | 49 return any(self.FeaturesDict[FpFeature] for FpFeature in ( |
| 46 'IsFP32', 'IsFP64', 'IsVec128')) | 50 'IsFP32', 'IsFP64', 'IsVec128')) |
| 47 | 51 |
| 48 class Reg(object): | 52 class Reg(object): |
| 49 def __init__(self, Name, Encode, **Features): | 53 def __init__(self, Name, Encode, AsmStr=None, **Features): |
| 50 self.Name = Name | 54 self.Name = Name |
| 51 self.Encode = Encode | 55 self.Encode = Encode |
| 52 self.Features = RegFeatures(**Features) | 56 if not AsmStr: |
| 57 AsmStr = '%s' % Name | |
| 58 self.Features = RegFeatures(AsmStr=AsmStr, **Features) | |
| 53 | 59 |
| 54 def __str__(self): | 60 def __str__(self): |
| 55 return 'Reg_{Name}, {Encode}, {Features}'.format(Name=self.Name, | 61 return 'Reg_{Name}, {Encode}, {Features}'.format(Name=self.Name, |
| 56 Encode=self.Encode, Features=self.Features) | 62 Encode=self.Encode, Features=self.Features) |
| 57 | 63 |
| 58 def IsAnAliasOf(self, Other): | 64 def IsAnAliasOf(self, Other): |
| 59 return self.Name in self.Features.Aliases().Aliases | 65 return self.Name in self.Features.Aliases().Aliases |
| 60 | 66 |
| 61 # Note: The following tables break the usual 80-col on purpose -- it is easier | 67 # Note: The following tables break the usual 80-col on purpose -- it is easier |
| 62 # to read the register tables if each register entry is contained on a single | 68 # to read the register tables if each register entry is contained on a single |
| 63 # line. | 69 # line. |
| 64 GPRs = [ | 70 GPRs = [ |
| 65 Reg( 'r0', 0, IsScratch=1, IsInt=1, Aliases=RegAliases( 'r0', 'r0r1')), | 71 Reg( 'r0', 0, IsScratch=1, CCArg=1, IsInt=1, Aliases= 'r0, r 0r1'), |
| 66 Reg( 'r1', 1, IsScratch=1, IsInt=1, Aliases=RegAliases( 'r1', 'r0r1')), | 72 Reg( 'r1', 1, IsScratch=1, CCArg=2, IsInt=1, Aliases= 'r1, r 0r1'), |
| 67 Reg( 'r2', 2, IsScratch=1, IsInt=1, Aliases=RegAliases( 'r2', 'r2r3')), | 73 Reg( 'r2', 2, IsScratch=1, CCArg=3, IsInt=1, Aliases= 'r2, r 2r3'), |
| 68 Reg( 'r3', 3, IsScratch=1, IsInt=1, Aliases=RegAliases( 'r3', 'r2r3')), | 74 Reg( 'r3', 3, IsScratch=1, CCArg=4, IsInt=1, Aliases= 'r3, r 2r3'), |
| 69 Reg( 'r4', 4, IsPreserved=1, IsInt=1, Aliases=RegAliases( 'r4', 'r4r5')), | 75 Reg( 'r4', 4, IsPreserved=1, IsInt=1, Aliases= 'r4, r 4r5'), |
| 70 Reg( 'r5', 5, IsPreserved=1, IsInt=1, Aliases=RegAliases( 'r5', 'r4r5')), | 76 Reg( 'r5', 5, IsPreserved=1, IsInt=1, Aliases= 'r5, r 4r5'), |
| 71 Reg( 'r6', 6, IsPreserved=1, IsInt=1, Aliases=RegAliases( 'r6', 'r6r7')), | 77 Reg( 'r6', 6, IsPreserved=1, IsInt=1, Aliases= 'r6, r 6r7'), |
| 72 Reg( 'r7', 7, IsPreserved=1, IsInt=1, Aliases=RegAliases( 'r7', 'r6r7')), | 78 Reg( 'r7', 7, IsPreserved=1, IsInt=1, Aliases= 'r7, r 6r7'), |
| 73 Reg( 'r8', 8, IsPreserved=1, IsInt=1, Aliases=RegAliases( 'r8', 'r8r9')), | 79 Reg( 'r8', 8, IsPreserved=1, IsInt=1, Aliases= 'r8, r 8r9'), |
| 74 Reg( 'r9', 9, IsPreserved=1, IsInt=0, Aliases=RegAliases( 'r9', 'r8r9')), | 80 Reg( 'r9', 9, IsPreserved=1, IsInt=0, Aliases= 'r9, r 8r9'), |
| 75 Reg('r10', 10, IsPreserved=1, IsInt=1, Aliases=RegAliases('r10', 'r10fp')), | 81 Reg('r10', 10, IsPreserved=1, IsInt=1, Aliases='r10, r1 0fp'), |
| 76 Reg( 'fp', 11, IsPreserved=1, IsInt=1, IsFramePtr=1, Aliases=RegAliases( 'fp', 'r10fp')), | 82 Reg( 'fp', 11, IsPreserved=1, IsInt=1, IsFramePtr=1, Aliases= 'fp, r1 0fp'), |
| 77 Reg( 'ip', 12, IsScratch=1, IsInt=1, Aliases=RegAliases( 'ip') ), | 83 Reg( 'ip', 12, IsScratch=1, IsInt=0, Aliases= 'ip'), |
| 78 Reg( 'sp', 13, IsScratch=0, IsInt=0, IsStackPtr=1, Aliases=RegAliases( 'sp') ), | 84 Reg( 'sp', 13, IsScratch=0, IsInt=0, IsStackPtr=1, Aliases= 'sp'), |
| 79 Reg( 'lr', 14, IsScratch=0, IsInt=0, Aliases=RegAliases( 'lr') ), | 85 Reg( 'lr', 14, IsScratch=0, IsInt=0, Aliases= 'lr'), |
| 80 Reg( 'pc', 15, IsScratch=0, IsInt=0, Aliases=RegAliases( 'pc') ), | 86 Reg( 'pc', 15, IsScratch=0, IsInt=0, Aliases= 'pc'), |
| 81 ] | 87 ] |
| 82 | 88 |
| 83 I64Pairs = [ | 89 I64Pairs = [ |
| 84 Reg( 'r0r1', 0, IsScratch=1, IsI64Pair=1, Aliases=RegAliases( 'r0r1', 'r0' , 'r1')), | 90 Reg( 'r0r1', 0, AsmStr= 'r0, r1', IsScratch=1, CCArg=1, IsI64Pair=1, Aliase s= 'r0r1, r0, r1'), |
| 85 Reg( 'r2r3', 2, IsScratch=1, IsI64Pair=1, Aliases=RegAliases( 'r2r3', 'r2' , 'r3')), | 91 Reg( 'r2r3', 2, AsmStr= 'r2, r3', IsScratch=1, CCArg=2, IsI64Pair=1, Aliase s= 'r2r3, r2, r3'), |
| 86 Reg( 'r4r5', 4, IsPreserved=1, IsI64Pair=1, Aliases=RegAliases( 'r4r5', 'r4' , 'r5')), | 92 Reg( 'r4r5', 4, AsmStr= 'r4, r5', IsPreserved=1, IsI64Pair=1, Aliase s= 'r4r5, r4, r5'), |
| 87 Reg( 'r6r7', 6, IsPreserved=1, IsI64Pair=1, Aliases=RegAliases( 'r6r7', 'r6' , 'r7')), | 93 Reg( 'r6r7', 6, AsmStr= 'r6, r7', IsPreserved=1, IsI64Pair=1, Aliase s= 'r6r7, r6, r7'), |
| 88 Reg( 'r8r9', 8, IsPreserved=1, IsI64Pair=0, Aliases=RegAliases( 'r8r9', 'r8' , 'r9')), | 94 Reg( 'r8r9', 8, AsmStr= 'r8, r9', IsPreserved=1, IsI64Pair=0, Aliase s= 'r8r9, r8, r9'), |
| 89 Reg('r10fp', 10, IsPreserved=1, IsI64Pair=1, Aliases=RegAliases('r10fp', 'r10' , 'fp')), | 95 Reg('r10fp', 10, AsmStr='r10, fp', IsPreserved=1, IsI64Pair=0, Aliase s='r10fp, r10, fp'), |
| 90 ] | 96 ] |
| 91 | 97 |
| 92 FP32 = [ | 98 FP32 = [ |
| 93 Reg( 's0', 0, IsScratch=1, IsFP32=1, Aliases=RegAliases( 's0', 'd0' , 'q0') ), | 99 Reg( 's0', 0, IsScratch=1, CCArg=1, IsFP32=1, Aliases= 's0, d0 , q0'), |
| 94 Reg( 's1', 1, IsScratch=1, IsFP32=1, Aliases=RegAliases( 's1', 'd0' , 'q0') ), | 100 Reg( 's1', 1, IsScratch=1, CCArg=2, IsFP32=1, Aliases= 's1, d0 , q0'), |
| 95 Reg( 's2', 2, IsScratch=1, IsFP32=1, Aliases=RegAliases( 's2', 'd1' , 'q0') ), | 101 Reg( 's2', 2, IsScratch=1, CCArg=3, IsFP32=1, Aliases= 's2, d1 , q0'), |
| 96 Reg( 's3', 3, IsScratch=1, IsFP32=1, Aliases=RegAliases( 's3', 'd1' , 'q0') ), | 102 Reg( 's3', 3, IsScratch=1, CCArg=4, IsFP32=1, Aliases= 's3, d1 , q0'), |
| 97 Reg( 's4', 4, IsScratch=1, IsFP32=1, Aliases=RegAliases( 's4', 'd2' , 'q1') ), | 103 Reg( 's4', 4, IsScratch=1, CCArg=5, IsFP32=1, Aliases= 's4, d2 , q1'), |
| 98 Reg( 's5', 5, IsScratch=1, IsFP32=1, Aliases=RegAliases( 's5', 'd2' , 'q1') ), | 104 Reg( 's5', 5, IsScratch=1, CCArg=6, IsFP32=1, Aliases= 's5, d2 , q1'), |
| 99 Reg( 's6', 6, IsScratch=1, IsFP32=1, Aliases=RegAliases( 's6', 'd3' , 'q1') ), | 105 Reg( 's6', 6, IsScratch=1, CCArg=7, IsFP32=1, Aliases= 's6, d3 , q1'), |
| 100 Reg( 's7', 7, IsScratch=1, IsFP32=1, Aliases=RegAliases( 's7', 'd3' , 'q1') ), | 106 Reg( 's7', 7, IsScratch=1, CCArg=8, IsFP32=1, Aliases= 's7, d3 , q1'), |
| 101 Reg( 's8', 8, IsScratch=1, IsFP32=1, Aliases=RegAliases( 's8', 'd4' , 'q2') ), | 107 Reg( 's8', 8, IsScratch=1, CCArg=9, IsFP32=1, Aliases= 's8, d4 , q2'), |
| 102 Reg( 's9', 9, IsScratch=1, IsFP32=1, Aliases=RegAliases( 's9', 'd4' , 'q2') ), | 108 Reg( 's9', 9, IsScratch=1, CCArg=10, IsFP32=1, Aliases= 's9, d4 , q2'), |
| 103 Reg('s10', 10, IsScratch=1, IsFP32=1, Aliases=RegAliases('s10', 'd5' , 'q2') ), | 109 Reg('s10', 10, IsScratch=1, CCArg=11, IsFP32=1, Aliases='s10, d5 , q2'), |
| 104 Reg('s11', 11, IsScratch=1, IsFP32=1, Aliases=RegAliases('s11', 'd5' , 'q2') ), | 110 Reg('s11', 11, IsScratch=1, CCArg=12, IsFP32=1, Aliases='s11, d5 , q2'), |
| 105 Reg('s12', 12, IsScratch=1, IsFP32=1, Aliases=RegAliases('s12', 'd6' , 'q3') ), | 111 Reg('s12', 12, IsScratch=1, CCArg=13, IsFP32=1, Aliases='s12, d6 , q3'), |
| 106 Reg('s13', 13, IsScratch=1, IsFP32=1, Aliases=RegAliases('s13', 'd6' , 'q3') ), | 112 Reg('s13', 13, IsScratch=1, CCArg=14, IsFP32=1, Aliases='s13, d6 , q3'), |
| 107 Reg('s14', 14, IsScratch=1, IsFP32=1, Aliases=RegAliases('s14', 'd7' , 'q3') ), | 113 Reg('s14', 14, IsScratch=1, CCArg=15, IsFP32=1, Aliases='s14, d7 , q3'), |
| 108 Reg('s15', 15, IsScratch=1, IsFP32=1, Aliases=RegAliases('s15', 'd7' , 'q3') ), | 114 Reg('s15', 15, IsScratch=1, CCArg=16, IsFP32=1, Aliases='s15, d7 , q3'), |
| 109 Reg('s16', 16, IsPreserved=1, IsFP32=1, Aliases=RegAliases('s16', 'd8' , 'q4') ), | 115 Reg('s16', 16, IsPreserved=1, IsFP32=1, Aliases='s16, d8 , q4'), |
| 110 Reg('s17', 17, IsPreserved=1, IsFP32=1, Aliases=RegAliases('s17', 'd8' , 'q4') ), | 116 Reg('s17', 17, IsPreserved=1, IsFP32=1, Aliases='s17, d8 , q4'), |
| 111 Reg('s18', 18, IsPreserved=1, IsFP32=1, Aliases=RegAliases('s18', 'd9' , 'q4') ), | 117 Reg('s18', 18, IsPreserved=1, IsFP32=1, Aliases='s18, d9 , q4'), |
| 112 Reg('s19', 19, IsPreserved=1, IsFP32=1, Aliases=RegAliases('s19', 'd9' , 'q4') ), | 118 Reg('s19', 19, IsPreserved=1, IsFP32=1, Aliases='s19, d9 , q4'), |
| 113 Reg('s20', 20, IsPreserved=1, IsFP32=1, Aliases=RegAliases('s20', 'd10', 'q5') ), | 119 Reg('s20', 20, IsPreserved=1, IsFP32=1, Aliases='s20, d10, q5'), |
| 114 Reg('s21', 21, IsPreserved=1, IsFP32=1, Aliases=RegAliases('s21', 'd10', 'q5') ), | 120 Reg('s21', 21, IsPreserved=1, IsFP32=1, Aliases='s21, d10, q5'), |
| 115 Reg('s22', 22, IsPreserved=1, IsFP32=1, Aliases=RegAliases('s22', 'd11', 'q5') ), | 121 Reg('s22', 22, IsPreserved=1, IsFP32=1, Aliases='s22, d11, q5'), |
| 116 Reg('s23', 23, IsPreserved=1, IsFP32=1, Aliases=RegAliases('s23', 'd11', 'q5') ), | 122 Reg('s23', 23, IsPreserved=1, IsFP32=1, Aliases='s23, d11, q5'), |
| 117 Reg('s24', 24, IsPreserved=1, IsFP32=1, Aliases=RegAliases('s24', 'd12', 'q6') ), | 123 Reg('s24', 24, IsPreserved=1, IsFP32=1, Aliases='s24, d12, q6'), |
| 118 Reg('s25', 25, IsPreserved=1, IsFP32=1, Aliases=RegAliases('s25', 'd12', 'q6') ), | 124 Reg('s25', 25, IsPreserved=1, IsFP32=1, Aliases='s25, d12, q6'), |
| 119 Reg('s26', 26, IsPreserved=1, IsFP32=1, Aliases=RegAliases('s26', 'd13', 'q6') ), | 125 Reg('s26', 26, IsPreserved=1, IsFP32=1, Aliases='s26, d13, q6'), |
| 120 Reg('s27', 27, IsPreserved=1, IsFP32=1, Aliases=RegAliases('s27', 'd13', 'q6') ), | 126 Reg('s27', 27, IsPreserved=1, IsFP32=1, Aliases='s27, d13, q6'), |
| 121 Reg('s28', 28, IsPreserved=1, IsFP32=1, Aliases=RegAliases('s28', 'd14', 'q7') ), | 127 Reg('s28', 28, IsPreserved=1, IsFP32=1, Aliases='s28, d14, q7'), |
| 122 Reg('s29', 29, IsPreserved=1, IsFP32=1, Aliases=RegAliases('s29', 'd14', 'q7') ), | 128 Reg('s29', 29, IsPreserved=1, IsFP32=1, Aliases='s29, d14, q7'), |
| 123 Reg('s30', 30, IsPreserved=1, IsFP32=1, Aliases=RegAliases('s30', 'd15', 'q7') ), | 129 Reg('s30', 30, IsPreserved=1, IsFP32=1, Aliases='s30, d15, q7'), |
| 124 Reg('s31', 31, IsPreserved=1, IsFP32=1, Aliases=RegAliases('s31', 'd14', 'q7') ), | 130 Reg('s31', 31, IsPreserved=1, IsFP32=1, Aliases='s31, d14, q7'), |
| 125 ] | 131 ] |
| 126 | 132 |
| 127 FP64 = [ | 133 FP64 = [ |
| 128 Reg( 'd0', 0, IsScratch=1, IsFP64=1, Aliases=RegAliases( 'd0', 'q0', 's0' , 's1')), | 134 Reg( 'd0', 0, IsScratch=1, CCArg=1, IsFP64=1, Aliases= 'd0, q0, s0, s1') , |
| 129 Reg( 'd1', 1, IsScratch=1, IsFP64=1, Aliases=RegAliases( 'd1', 'q0', 's2' , 's3')), | 135 Reg( 'd1', 1, IsScratch=1, CCArg=2, IsFP64=1, Aliases= 'd1, q0, s2, s3') , |
| 130 Reg( 'd2', 2, IsScratch=1, IsFP64=1, Aliases=RegAliases( 'd2', 'q1', 's4' , 's5')), | 136 Reg( 'd2', 2, IsScratch=1, CCArg=3, IsFP64=1, Aliases= 'd2, q1, s4, s5') , |
| 131 Reg( 'd3', 3, IsScratch=1, IsFP64=1, Aliases=RegAliases( 'd3', 'q1', 's6' , 's7')), | 137 Reg( 'd3', 3, IsScratch=1, CCArg=4, IsFP64=1, Aliases= 'd3, q1, s6, s7') , |
| 132 Reg( 'd4', 4, IsScratch=1, IsFP64=1, Aliases=RegAliases( 'd4', 'q2', 's8' , 's9')), | 138 Reg( 'd4', 4, IsScratch=1, CCArg=5, IsFP64=1, Aliases= 'd4, q2, s8, s9') , |
| 133 Reg( 'd5', 5, IsScratch=1, IsFP64=1, Aliases=RegAliases( 'd5', 'q2', 's10' , 's11')), | 139 Reg( 'd5', 5, IsScratch=1, CCArg=6, IsFP64=1, Aliases= 'd5, q2, s10, s11') , |
| 134 Reg( 'd6', 6, IsScratch=1, IsFP64=1, Aliases=RegAliases( 'd6', 'q3', 's12' , 's13')), | 140 Reg( 'd6', 6, IsScratch=1, CCArg=7, IsFP64=1, Aliases= 'd6, q3, s12, s13') , |
| 135 Reg( 'd7', 7, IsScratch=1, IsFP64=1, Aliases=RegAliases( 'd7', 'q3', 's14' , 's15')), | 141 Reg( 'd7', 7, IsScratch=1, CCArg=8, IsFP64=1, Aliases= 'd7, q3, s14, s15') , |
| 136 Reg( 'd8', 8, IsPreserved=1, IsFP64=1, Aliases=RegAliases( 'd8', 'q4', 's16' , 's17')), | 142 Reg( 'd8', 8, IsPreserved=1, IsFP64=1, Aliases= 'd8, q4, s16, s17') , |
| 137 Reg( 'd9', 9, IsPreserved=1, IsFP64=1, Aliases=RegAliases( 'd9', 'q4', 's18' , 's19')), | 143 Reg( 'd9', 9, IsPreserved=1, IsFP64=1, Aliases= 'd9, q4, s18, s19') , |
| 138 Reg('d10', 10, IsPreserved=1, IsFP64=1, Aliases=RegAliases('d10', 'q5', 's20' , 's21')), | 144 Reg('d10', 10, IsPreserved=1, IsFP64=1, Aliases='d10, q5, s20, s21') , |
| 139 Reg('d11', 11, IsPreserved=1, IsFP64=1, Aliases=RegAliases('d11', 'q5', 's22' , 's24')), | 145 Reg('d11', 11, IsPreserved=1, IsFP64=1, Aliases='d11, q5, s22, s24') , |
| 140 Reg('d12', 12, IsPreserved=1, IsFP64=1, Aliases=RegAliases('d12', 'q6', 's24' , 's25')), | 146 Reg('d12', 12, IsPreserved=1, IsFP64=1, Aliases='d12, q6, s24, s25') , |
| 141 Reg('d13', 13, IsPreserved=1, IsFP64=1, Aliases=RegAliases('d13', 'q6', 's26' , 's27')), | 147 Reg('d13', 13, IsPreserved=1, IsFP64=1, Aliases='d13, q6, s26, s27') , |
| 142 Reg('d14', 14, IsPreserved=1, IsFP64=1, Aliases=RegAliases('d14', 'q7', 's28' , 's28')), | 148 Reg('d14', 14, IsPreserved=1, IsFP64=1, Aliases='d14, q7, s28, s28') , |
| 143 Reg('d15', 15, IsPreserved=1, IsFP64=1, Aliases=RegAliases('d15', 'q7', 's30' , 's31')), | 149 Reg('d15', 15, IsPreserved=1, IsFP64=1, Aliases='d15, q7, s30, s31') , |
| 144 Reg('d16', 16, IsScratch=1, IsFP64=1, Aliases=RegAliases('d16', 'q8')), | 150 Reg('d16', 16, IsScratch=1, IsFP64=1, Aliases='d16, q8'), |
| 145 Reg('d17', 17, IsScratch=1, IsFP64=1, Aliases=RegAliases('d17', 'q8')), | 151 Reg('d17', 17, IsScratch=1, IsFP64=1, Aliases='d17, q8'), |
| 146 Reg('d18', 18, IsScratch=1, IsFP64=1, Aliases=RegAliases('d18', 'q9')), | 152 Reg('d18', 18, IsScratch=1, IsFP64=1, Aliases='d18, q9'), |
| 147 Reg('d19', 19, IsScratch=1, IsFP64=1, Aliases=RegAliases('d19', 'q9')), | 153 Reg('d19', 19, IsScratch=1, IsFP64=1, Aliases='d19, q9'), |
| 148 Reg('d20', 20, IsScratch=1, IsFP64=1, Aliases=RegAliases('d20', 'q10')), | 154 Reg('d20', 20, IsScratch=1, IsFP64=1, Aliases='d20, q10'), |
| 149 Reg('d21', 21, IsScratch=1, IsFP64=1, Aliases=RegAliases('d21', 'q10')), | 155 Reg('d21', 21, IsScratch=1, IsFP64=1, Aliases='d21, q10'), |
| 150 Reg('d22', 22, IsScratch=1, IsFP64=1, Aliases=RegAliases('d22', 'q11')), | 156 Reg('d22', 22, IsScratch=1, IsFP64=1, Aliases='d22, q11'), |
| 151 Reg('d23', 23, IsScratch=1, IsFP64=1, Aliases=RegAliases('d23', 'q11')), | 157 Reg('d23', 23, IsScratch=1, IsFP64=1, Aliases='d23, q11'), |
| 152 Reg('d24', 24, IsScratch=1, IsFP64=1, Aliases=RegAliases('d24', 'q12')), | 158 Reg('d24', 24, IsScratch=1, IsFP64=1, Aliases='d24, q12'), |
| 153 Reg('d25', 25, IsScratch=1, IsFP64=1, Aliases=RegAliases('d25', 'q12')), | 159 Reg('d25', 25, IsScratch=1, IsFP64=1, Aliases='d25, q12'), |
| 154 Reg('d26', 26, IsScratch=1, IsFP64=1, Aliases=RegAliases('d26', 'q13')), | 160 Reg('d26', 26, IsScratch=1, IsFP64=1, Aliases='d26, q13'), |
| 155 Reg('d27', 27, IsScratch=1, IsFP64=1, Aliases=RegAliases('d27', 'q13')), | 161 Reg('d27', 27, IsScratch=1, IsFP64=1, Aliases='d27, q13'), |
| 156 Reg('d28', 28, IsScratch=1, IsFP64=1, Aliases=RegAliases('d28', 'q14')), | 162 Reg('d28', 28, IsScratch=1, IsFP64=1, Aliases='d28, q14'), |
| 157 Reg('d29', 29, IsScratch=1, IsFP64=1, Aliases=RegAliases('d29', 'q14')), | 163 Reg('d29', 29, IsScratch=1, IsFP64=1, Aliases='d29, q14'), |
| 158 Reg('d30', 30, IsScratch=1, IsFP64=1, Aliases=RegAliases('d30', 'q15')), | 164 Reg('d30', 30, IsScratch=1, IsFP64=1, Aliases='d30, q15'), |
| 159 Reg('d31', 31, IsScratch=1, IsFP64=1, Aliases=RegAliases('d31', 'q15')), | 165 Reg('d31', 31, IsScratch=1, IsFP64=1, Aliases='d31, q15'), |
| 160 ] | 166 ] |
| 161 | 167 |
| 162 Vec128 = [ | 168 Vec128 = [ |
| 163 Reg( 'q0', 0, IsScratch=1, IsVec128=1, Aliases=RegAliases( 'q0', 'd0', 'd 1', 's0', 's1', 's2', 's3')), | 169 Reg( 'q0', 0, IsScratch=1, CCArg=1, IsVec128=1, Aliases= 'q0, d0, d1, s0 , s1, s2, s3'), |
| 164 Reg( 'q1', 1, IsScratch=1, IsVec128=1, Aliases=RegAliases( 'q1', 'd2', 'd 3', 's4', 's5', 's6', 's7')), | 170 Reg( 'q1', 1, IsScratch=1, CCArg=2, IsVec128=1, Aliases= 'q1, d2, d3, s4 , s5, s6, s7'), |
| 165 Reg( 'q2', 2, IsScratch=1, IsVec128=1, Aliases=RegAliases( 'q2', 'd4', 'd 5', 's8', 's9', 's10', 's11')), | 171 Reg( 'q2', 2, IsScratch=1, CCArg=3, IsVec128=1, Aliases= 'q2, d4, d5, s8 , s9, s10, s11'), |
| 166 Reg( 'q3', 3, IsScratch=1, IsVec128=1, Aliases=RegAliases( 'q3', 'd6', 'd 7', 's12', 's13', 's14', 's15')), | 172 Reg( 'q3', 3, IsScratch=1, CCArg=4, IsVec128=1, Aliases= 'q3, d6, d7, s12 , s13, s14, s15'), |
| 167 Reg( 'q4', 4, IsPreserved=1, IsVec128=1, Aliases=RegAliases( 'q4', 'd8', 'd 9', 's16', 's17', 's18', 's19')), | 173 Reg( 'q4', 4, IsPreserved=1, IsVec128=1, Aliases= 'q4, d8, d9, s16 , s17, s18, s19'), |
| 168 Reg( 'q5', 5, IsPreserved=1, IsVec128=1, Aliases=RegAliases( 'q5', 'd10', 'd1 1', 's20', 's21', 's22', 's23')), | 174 Reg( 'q5', 5, IsPreserved=1, IsVec128=1, Aliases= 'q5, d10, d11, s20 , s21, s22, s23'), |
| 169 Reg( 'q6', 6, IsPreserved=1, IsVec128=1, Aliases=RegAliases( 'q6', 'd12', 'd1 3', 's24', 's25', 's26', 's27')), | 175 Reg( 'q6', 6, IsPreserved=1, IsVec128=1, Aliases= 'q6, d12, d13, s24 , s25, s26, s27'), |
| 170 Reg( 'q7', 7, IsPreserved=1, IsVec128=1, Aliases=RegAliases( 'q7', 'd14', 'd1 5', 's28', 's29', 's30', 's31')), | 176 Reg( 'q7', 7, IsPreserved=1, IsVec128=1, Aliases= 'q7, d14, d15, s28 , s29, s30, s31'), |
| 171 Reg( 'q8', 8, IsScratch=1, IsVec128=1, Aliases=RegAliases( 'q8', 'd16', 'd1 7')), | 177 Reg( 'q8', 8, IsScratch=1, IsVec128=1, Aliases= 'q8, d16, d17'), |
| 172 Reg( 'q9', 9, IsScratch=1, IsVec128=1, Aliases=RegAliases( 'q9', 'd18', 'd1 9')), | 178 Reg( 'q9', 9, IsScratch=1, IsVec128=1, Aliases= 'q9, d18, d19'), |
| 173 Reg('q10', 10, IsScratch=1, IsVec128=1, Aliases=RegAliases('q10', 'd20', 'd2 1')), | 179 Reg('q10', 10, IsScratch=1, IsVec128=1, Aliases='q10, d20, d21'), |
| 174 Reg('q11', 11, IsScratch=1, IsVec128=1, Aliases=RegAliases('q11', 'd22', 'd2 3')), | 180 Reg('q11', 11, IsScratch=1, IsVec128=1, Aliases='q11, d22, d23'), |
| 175 Reg('q12', 12, IsScratch=1, IsVec128=1, Aliases=RegAliases('q12', 'd24', 'd2 5')), | 181 Reg('q12', 12, IsScratch=1, IsVec128=1, Aliases='q12, d24, d25'), |
| 176 Reg('q13', 13, IsScratch=1, IsVec128=1, Aliases=RegAliases('q13', 'd26', 'd2 7')), | 182 Reg('q13', 13, IsScratch=1, IsVec128=1, Aliases='q13, d26, d27'), |
| 177 Reg('q14', 14, IsScratch=1, IsVec128=1, Aliases=RegAliases('q14', 'd28', 'd2 9')), | 183 Reg('q14', 14, IsScratch=1, IsVec128=1, Aliases='q14, d28, d29'), |
| 178 Reg('q15', 15, IsScratch=1, IsVec128=1, Aliases=RegAliases('q15', 'd30', 'd3 1')), | 184 Reg('q15', 15, IsScratch=1, IsVec128=1, Aliases='q15, d30, d31'), |
| 179 ] | 185 ] |
| 180 | 186 |
| 181 def _reverse(x): | 187 def _reverse(x): |
| 182 return sorted(x, key=lambda x: x.Encode, reverse=True) | 188 return sorted(x, key=lambda x: x.Encode, reverse=True) |
| 183 RegClasses = [GPRs, I64Pairs, FP32, _reverse(FP64), _reverse(Vec128)] | 189 |
| 190 RegClasses = [('GPR', GPRs), ('I64PAIR', I64Pairs), ('FP32', FP32), | |
| 191 ('FP64', _reverse(FP64)), ('VEC128', _reverse(Vec128))] | |
| 184 | 192 |
| 185 AllRegs = {} | 193 AllRegs = {} |
| 186 for RegClass in RegClasses: | 194 for _, RegClass in RegClasses: |
| 187 for Reg in RegClass: | 195 for Reg in RegClass: |
| 188 assert Reg.Name not in AllRegs | 196 assert Reg.Name not in AllRegs |
| 189 AllRegs[Reg.Name] = Reg | 197 AllRegs[Reg.Name] = Reg |
| 190 | 198 |
| 191 for RegClass in RegClasses: | 199 for _, RegClass in RegClasses: |
| 192 for Reg in RegClass: | 200 for Reg in RegClass: |
| 193 for Alias in AllRegs[Reg.Name].Features.Aliases().Aliases: | 201 for Alias in AllRegs[Reg.Name].Features.Aliases().Aliases: |
| 194 assert AllRegs[Alias].IsAnAliasOf(Reg), '%s VS %s' % (Reg, AllRegs[Alias]) | 202 assert AllRegs[Alias].IsAnAliasOf(Reg), '%s VS %s' % (Reg, AllRegs[Alias]) |
| 195 assert AllRegs[Alias].IsAnAliasOf(Reg), '%s VS %s' % (Reg, AllRegs[Alias]) | 203 assert AllRegs[Alias].IsAnAliasOf(Reg), '%s VS %s' % (Reg, AllRegs[Alias]) |
| 196 assert (AllRegs[Alias].Features.LivesInGPR() == | 204 assert (AllRegs[Alias].Features.LivesInGPR() == |
| 197 Reg.Features.LivesInGPR()), '%s VS %s' % (Reg, AllRegs[Alias]) | 205 Reg.Features.LivesInGPR()), '%s VS %s' % (Reg, AllRegs[Alias]) |
| 198 assert (AllRegs[Alias].Features.LivesInVFP() == | 206 assert (AllRegs[Alias].Features.LivesInVFP() == |
| 199 Reg.Features.LivesInVFP()), '%s VS %s' % (Reg, AllRegs[Alias]) | 207 Reg.Features.LivesInVFP()), '%s VS %s' % (Reg, AllRegs[Alias]) |
| 200 | 208 |
| 201 for RegClass in RegClasses: | 209 print ("// This file was auto generated by the gen_arm32_reg_tables.py script. " |
|
Jim Stichnoth
2015/12/11 21:22:10
It would be extra cool if the "gen_arm32_reg_table
John
2015/12/16 15:51:14
Done.
| |
| 210 "Do not\n" | |
| 211 "// modify it: modify the script instead.\n" | |
| 212 "\n" | |
| 213 "#ifndef SUBZERO_SRC_ICEREGISTERSARM32_DEF\n" | |
| 214 "#define SUBZERO_SRC_ICEREGISTERSARM32_DEF\n") | |
| 215 | |
| 216 for Name, RegClass in RegClasses: | |
| 217 print "#define REGARM32_%s_TABLE" % Name, | |
| 202 for Reg in RegClass: | 218 for Reg in RegClass: |
| 203 print 'X({Reg})'.format(Reg=Reg) | 219 print '\\\n X({Reg})'.format(Reg=Reg), |
| 204 print | 220 print '\n' |
| 221 print "#endif // SUBZERO_SRC_ICEREGISTERSARM32_DEF", | |
| OLD | NEW |
