Add DMB instruction to the ARM integrated assembler.

src/IceAssemblerARM32.cpp

Index: src/IceAssemblerARM32.cpp
diff --git a/src/IceAssemblerARM32.cpp b/src/IceAssemblerARM32.cpp
index 9077325a0acbf05838bc11da4c789a4bb74803f5..8db0ddc87df5817ef57ffd43e0157951d90fdf0e 100644
--- a/src/IceAssemblerARM32.cpp
+++ b/src/IceAssemblerARM32.cpp
@@ -45,6 +45,10 @@ static constexpr IValueT B12 = 1 << 12;
 static constexpr IValueT B13 = 1 << 13;
 static constexpr IValueT B14 = 1 << 14;
 static constexpr IValueT B15 = 1 << 15;
+static constexpr IValueT B16 = 1 << 16;
+static constexpr IValueT B17 = 1 << 17;
+static constexpr IValueT B18 = 1 << 18;
+static constexpr IValueT B19 = 1 << 19;
 static constexpr IValueT B20 = 1 << 20;
 static constexpr IValueT B21 = 1 << 21;
 static constexpr IValueT B22 = 1 << 22;
@@ -1077,6 +1081,20 @@ void AssemblerARM32::cmp(const Operand *OpRn, const Operand *OpSrc1,
   emitCompareOp(Cond, CmpOpcode, OpRn, OpSrc1, CmpName);
 }
 
+void AssemblerARM32::dmb(IValueT Option) {
+  // DMB - ARM section A8.8.43, encoding A1:
+  //   dmb <option>
+  //
+  // 1111010101111111111100000101xxxx where xxxx=Option.
+  assert(Utils::IsUint(4, Option) && "Bad dmb option");
+  AssemblerBuffer::EnsureCapacity ensured(&Buffer);
+  const IValueT Encoding =
+      (encodeCondition(CondARM32::kNone) << kConditionShift) | B26 | B24 | B22 |
+      B21 | B20 | B19 | B18 | B17 | B16 | B15 | B14 | B13 | B12 | B6 | B4 |
+      Option;
+  emitInst(Encoding);
+}
+
 void AssemblerARM32::eor(const Operand *OpRd, const Operand *OpRn,
                          const Operand *OpSrc1, bool SetFlags,
                          CondARM32::Cond Cond) {