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Side by Side Diff: src/IceAssemblerARM32.h

Issue 1507873004: Add DMB instruction to the ARM integrated assembler. (Closed) Base URL: https://chromium.googlesource.com/native_client/pnacl-subzero.git@master
Patch Set: Fix comment. Created 5 years ago
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1 //===- subzero/src/IceAssemblerARM32.h - Assembler for ARM32 ----*- C++ -*-===// 1 //===- subzero/src/IceAssemblerARM32.h - Assembler for ARM32 ----*- C++ -*-===//
2 // 2 //
3 // Copyright (c) 2013, the Dart project authors. Please see the AUTHORS file 3 // Copyright (c) 2013, the Dart project authors. Please see the AUTHORS file
4 // for details. All rights reserved. Use of this source code is governed by a 4 // for details. All rights reserved. Use of this source code is governed by a
5 // BSD-style license that can be found in the LICENSE file. 5 // BSD-style license that can be found in the LICENSE file.
6 // 6 //
7 // Modified by the Subzero authors. 7 // Modified by the Subzero authors.
8 // 8 //
9 //===----------------------------------------------------------------------===// 9 //===----------------------------------------------------------------------===//
10 // 10 //
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202 void bl(const ConstantRelocatable *Target); 202 void bl(const ConstantRelocatable *Target);
203 203
204 void blx(const Operand *Target); 204 void blx(const Operand *Target);
205 205
206 void bx(RegARM32::GPRRegister Rm, CondARM32::Cond Cond = CondARM32::AL); 206 void bx(RegARM32::GPRRegister Rm, CondARM32::Cond Cond = CondARM32::AL);
207 207
208 void cmn(const Operand *OpRn, const Operand *OpSrc1, CondARM32::Cond Cond); 208 void cmn(const Operand *OpRn, const Operand *OpSrc1, CondARM32::Cond Cond);
209 209
210 void cmp(const Operand *OpRn, const Operand *OpSrc1, CondARM32::Cond Cond); 210 void cmp(const Operand *OpRn, const Operand *OpSrc1, CondARM32::Cond Cond);
211 211
212 void dmb(IValueT Option); // Option is a 4-bit value.
213
212 void eor(const Operand *OpRd, const Operand *OpRn, const Operand *OpSrc1, 214 void eor(const Operand *OpRd, const Operand *OpRn, const Operand *OpSrc1,
213 bool SetFlags, CondARM32::Cond Cond); 215 bool SetFlags, CondARM32::Cond Cond);
214 216
215 void ldr(const Operand *OpRt, const Operand *OpAddress, CondARM32::Cond Cond, 217 void ldr(const Operand *OpRt, const Operand *OpAddress, CondARM32::Cond Cond,
216 const TargetInfo &TInfo); 218 const TargetInfo &TInfo);
217 219
218 void ldr(const Operand *OpRt, const Operand *OpAddress, CondARM32::Cond Cond, 220 void ldr(const Operand *OpRt, const Operand *OpAddress, CondARM32::Cond Cond,
219 const TargetLowering *Lowering) { 221 const TargetLowering *Lowering) {
220 const TargetInfo TInfo(Lowering); 222 const TargetInfo TInfo(Lowering);
221 ldr(OpRt, OpAddress, Cond, TInfo); 223 ldr(OpRt, OpAddress, Cond, TInfo);
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418 // where cccc=Cond, xxxxxxx<<21=Opcode, dddd=Rd, s=SetFlags, and 420 // where cccc=Cond, xxxxxxx<<21=Opcode, dddd=Rd, s=SetFlags, and
419 // iiiiiiiiiiiiiiii=Imm16. 421 // iiiiiiiiiiiiiiii=Imm16.
420 void emitMovwt(CondARM32::Cond Cond, bool IsMovw, const Operand *OpRd, 422 void emitMovwt(CondARM32::Cond Cond, bool IsMovw, const Operand *OpRd,
421 const Operand *OpSrc, const char *MovName); 423 const Operand *OpSrc, const char *MovName);
422 }; 424 };
423 425
424 } // end of namespace ARM32 426 } // end of namespace ARM32
425 } // end of namespace Ice 427 } // end of namespace Ice
426 428
427 #endif // SUBZERO_SRC_ICEASSEMBLERARM32_H 429 #endif // SUBZERO_SRC_ICEASSEMBLERARM32_H
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