Add DMB instruction to the ARM integrated assembler.

src/IceAssemblerARM32.cpp

 //===- subzero/src/IceAssemblerARM32.cpp - Assembler for ARM32 --*- C++ -*-===//
 //
 // Copyright (c) 2013, the Dart project authors.  Please see the AUTHORS file
 // for details. All rights reserved. Use of this source code is governed by a
 // BSD-style license that can be found in the LICENSE file.
 //
 // Modified by the Subzero authors.
 //
 //===----------------------------------------------------------------------===//
 //
@@ skipping 27 matching lines @@
 static constexpr IValueT B2 = 1 << 2;
 static constexpr IValueT B3 = 1 << 3;
 static constexpr IValueT B4 = 1 << 4;
 static constexpr IValueT B5 = 1 << 5;
 static constexpr IValueT B6 = 1 << 6;
 static constexpr IValueT B7 = 1 << 7;
 static constexpr IValueT B12 = 1 << 12;
 static constexpr IValueT B13 = 1 << 13;
 static constexpr IValueT B14 = 1 << 14;
 static constexpr IValueT B15 = 1 << 15;
+static constexpr IValueT B16 = 1 << 16;
+static constexpr IValueT B17 = 1 << 17;
+static constexpr IValueT B18 = 1 << 18;
+static constexpr IValueT B19 = 1 << 19;
 static constexpr IValueT B20 = 1 << 20;
 static constexpr IValueT B21 = 1 << 21;
 static constexpr IValueT B22 = 1 << 22;
 static constexpr IValueT B23 = 1 << 23;
 static constexpr IValueT B24 = 1 << 24;
 static constexpr IValueT B25 = 1 << 25;
 static constexpr IValueT B26 = 1 << 26;
 static constexpr IValueT B27 = 1 << 27;
 
 // Constants used for the decoding or encoding of the individual fields of
@@ skipping 1012 matching lines @@
   // CMP (immediate) - ARM section A8.8.37
   //  cmp<c: <Rn>, #<RotatedImm8>
   //
   // cccc00110101nnnn0000iiiiiiiiiiii where cccc=Cond, dddd=Rd, nnnn=Rn,
   // s=SetFlags and iiiiiiiiiiii=Src1Value defining RotatedImm8.
   constexpr const char *CmpName = "cmp";
   constexpr IValueT CmpOpcode = B3 | B1; // ie. 1010
   emitCompareOp(Cond, CmpOpcode, OpRn, OpSrc1, CmpName);
 }
 
+void AssemblerARM32::dmb(IValueT Option) {
+  // DMB - ARM section A8.8.43, encoding A1:
+  //   dmb <option>
+  //
+  // 1111010101111111111100000101xxxx where xxxx=Option.
+  assert(Utils::IsUint(4, Option) && "Bad dmb option");
+  AssemblerBuffer::EnsureCapacity ensured(&Buffer);
+  const IValueT Encoding =
+      (encodeCondition(CondARM32::kNone) << kConditionShift) | B26 | B24 | B22 |
+      B21 | B20 | B19 | B18 | B17 | B16 | B15 | B14 | B13 | B12 | B6 | B4 |
+      Option;
+  emitInst(Encoding);
+}
+
 void AssemblerARM32::eor(const Operand *OpRd, const Operand *OpRn,
                          const Operand *OpSrc1, bool SetFlags,
                          CondARM32::Cond Cond) {
   // EOR (register) - ARM section A*.8.47, encoding A1:
   //   eor{s}<c> <Rd>, <Rn>, <Rm>{, <shift>}
   //
   // cccc0000001snnnnddddiiiiitt0mmmm where cccc=Cond, dddd=Rd, nnnn=Rn,
   // mmmm=Rm, iiiii=Shift, tt=ShiftKind, and s=SetFlags.
   //
   // EOR (Immediate) - ARM section A8.*.46, encoding A1:
@@ skipping 568 matching lines @@
 
 void AssemblerARM32::uxt(const Operand *OpRd, const Operand *OpSrc0,
                          CondARM32::Cond Cond) {
   constexpr const char *UxtName = "uxt";
   constexpr IValueT UxtOpcode = B26 | B25 | B23 | B22 | B21;
   emitSignExtend(Cond, UxtOpcode, OpRd, OpSrc0, UxtName);
 }
 
 } // end of namespace ARM32
 } // end of namespace Ice