[test] Test expectations in cctest should use CHECK and not DCHECK.

test/cctest/test-assembler-arm64.cc

 // Copyright 2013 the V8 project authors. All rights reserved.
 // Redistribution and use in source and binary forms, with or without
 // modification, are permitted provided that the following conditions are
 // met:
 //
 //     * Redistributions of source code must retain the above copyright
 //       notice, this list of conditions and the following disclaimer.
 //     * Redistributions in binary form must reproduce the above
 //       copyright notice, this list of conditions and the following
 //       disclaimer in the documentation and/or other materials provided
@@ skipping 102 matching lines @@
 
 #define INIT_V8()                                                              \
   CcTest::InitializeVM();                                                      \
 
 #ifdef USE_SIMULATOR
 
 // Run tests with the simulator.
 #define SETUP_SIZE(buf_size)                                   \
   Isolate* isolate = CcTest::i_isolate();                      \
   HandleScope scope(isolate);                                  \
-  DCHECK(isolate != NULL);                                     \
+  CHECK(isolate != NULL);                                      \
   byte* buf = new byte[buf_size];                              \
   MacroAssembler masm(isolate, buf, buf_size,                  \
                       v8::internal::CodeObjectRequired::kYes); \
   Decoder<DispatchingDecoderVisitor>* decoder =                \
       new Decoder<DispatchingDecoderVisitor>();                \
   Simulator simulator(decoder);                                \
   PrintDisassembler* pdis = NULL;                              \
   RegisterDump core;
 
 /*  if (Cctest::trace_sim()) {                                                 \
@@ skipping 34 matching lines @@
 
 #define TEARDOWN()                                                             \
   delete pdis;                                                                 \
   delete[] buf;
 
 #else  // ifdef USE_SIMULATOR.
 // Run the test on real hardware or models.
 #define SETUP_SIZE(buf_size)                                   \
   Isolate* isolate = CcTest::i_isolate();                      \
   HandleScope scope(isolate);                                  \
-  DCHECK(isolate != NULL);                                     \
+  CHECK(isolate != NULL);                                      \
   byte* buf = new byte[buf_size];                              \
   MacroAssembler masm(isolate, buf, buf_size,                  \
                       v8::internal::CodeObjectRequired::kYes); \
   RegisterDump core;
 
 #define RESET()                                                                \
   __ Reset();                                                                  \
   /* Reset the machine state (like simulator.ResetState()). */                 \
   __ Msr(NZCV, xzr);                                                           \
   __ Msr(FPCR, xzr);
@@ skipping 38 matching lines @@
 #define CHECK_EQUAL_FP32(expected, result)                                    \
   CHECK(EqualFP32(expected, &core, result))
 
 #define CHECK_EQUAL_64(expected, result)                                      \
   CHECK(Equal64(expected, &core, result))
 
 #define CHECK_EQUAL_FP64(expected, result)                                    \
   CHECK(EqualFP64(expected, &core, result))
 
 #ifdef DEBUG
-#define DCHECK_LITERAL_POOL_SIZE(expected)                                     \
+#define CHECK_LITERAL_POOL_SIZE(expected) \
   CHECK((expected) == (__ LiteralPoolSize()))
 #else
-#define DCHECK_LITERAL_POOL_SIZE(expected)                                     \
-  ((void) 0)
+#define CHECK_LITERAL_POOL_SIZE(expected) ((void)0)
 #endif
 
 
 TEST(stack_ops) {
   INIT_V8();
   SETUP();
 
   START();
   // save csp.
   __ Mov(x29, csp);
@@ skipping 3045 matching lines @@
   CHECK_EQUAL_FP64(1.234, d13);
   CHECK_EQUAL_FP32(2.5, s25);
 
   TEARDOWN();
 }
 
 
 static void LdrLiteralRangeHelper(ptrdiff_t range_,
                                   LiteralPoolEmitOption option,
                                   bool expect_dump) {
-  DCHECK(range_ > 0);
+  CHECK(range_ > 0);
   SETUP_SIZE(range_ + 1024);
 
   Label label_1, label_2;
 
   size_t range = static_cast<size_t>(range_);
   size_t code_size = 0;
   size_t pool_guard_size;
 
   if (option == NoJumpRequired) {
     // Space for an explicit branch.
     pool_guard_size = sizeof(Instr);
   } else {
     pool_guard_size = 0;
   }
 
   START();
   // Force a pool dump so the pool starts off empty.
   __ EmitLiteralPool(JumpRequired);
-  DCHECK_LITERAL_POOL_SIZE(0);
+  CHECK_LITERAL_POOL_SIZE(0);
 
   __ Ldr(x0, 0x1234567890abcdefUL);
   __ Ldr(w1, 0xfedcba09);
   __ Ldr(d0, 1.234);
   __ Ldr(s1, 2.5);
-  DCHECK_LITERAL_POOL_SIZE(4);
+  CHECK_LITERAL_POOL_SIZE(4);
 
   code_size += 4 * sizeof(Instr);
 
   // Check that the requested range (allowing space for a branch over the pool)
   // can be handled by this test.
-  DCHECK((code_size + pool_guard_size) <= range);
+  CHECK((code_size + pool_guard_size) <= range);
 
   // Emit NOPs up to 'range', leaving space for the pool guard.
   while ((code_size + pool_guard_size) < range) {
     __ Nop();
     code_size += sizeof(Instr);
   }
 
   // Emit the guard sequence before the literal pool.
   if (option == NoJumpRequired) {
     __ B(&label_1);
     code_size += sizeof(Instr);
   }
 
-  DCHECK(code_size == range);
-  DCHECK_LITERAL_POOL_SIZE(4);
+  CHECK(code_size == range);
+  CHECK_LITERAL_POOL_SIZE(4);
 
   // Possibly generate a literal pool.
   __ CheckLiteralPool(option);
   __ Bind(&label_1);
   if (expect_dump) {
-    DCHECK_LITERAL_POOL_SIZE(0);
+    CHECK_LITERAL_POOL_SIZE(0);
   } else {
-    DCHECK_LITERAL_POOL_SIZE(4);
+    CHECK_LITERAL_POOL_SIZE(4);
   }
 
   // Force a pool flush to check that a second pool functions correctly.
   __ EmitLiteralPool(JumpRequired);
-  DCHECK_LITERAL_POOL_SIZE(0);
+  CHECK_LITERAL_POOL_SIZE(0);
 
   // These loads should be after the pool (and will require a new one).
   __ Ldr(x4, 0x34567890abcdef12UL);
   __ Ldr(w5, 0xdcba09fe);
   __ Ldr(d4, 123.4);
   __ Ldr(s5, 250.0);
-  DCHECK_LITERAL_POOL_SIZE(4);
+  CHECK_LITERAL_POOL_SIZE(4);
   END();
 
   RUN();
 
   // Check that the literals loaded correctly.
   CHECK_EQUAL_64(0x1234567890abcdefUL, x0);
   CHECK_EQUAL_64(0xfedcba09, x1);
   CHECK_EQUAL_FP64(1.234, d0);
   CHECK_EQUAL_FP32(2.5, s1);
   CHECK_EQUAL_64(0x34567890abcdef12UL, x4);
@@ skipping 2057 matching lines @@
 
 TEST(fmadd_fmsub_double_nans) {
   INIT_V8();
   // Make sure that NaN propagation works correctly.
   double s1 = rawbits_to_double(0x7ff5555511111111);
   double s2 = rawbits_to_double(0x7ff5555522222222);
   double sa = rawbits_to_double(0x7ff55555aaaaaaaa);
   double q1 = rawbits_to_double(0x7ffaaaaa11111111);
   double q2 = rawbits_to_double(0x7ffaaaaa22222222);
   double qa = rawbits_to_double(0x7ffaaaaaaaaaaaaa);
-  DCHECK(IsSignallingNaN(s1));
-  DCHECK(IsSignallingNaN(s2));
-  DCHECK(IsSignallingNaN(sa));
-  DCHECK(IsQuietNaN(q1));
-  DCHECK(IsQuietNaN(q2));
-  DCHECK(IsQuietNaN(qa));
+  CHECK(IsSignallingNaN(s1));
+  CHECK(IsSignallingNaN(s2));
+  CHECK(IsSignallingNaN(sa));
+  CHECK(IsQuietNaN(q1));
+  CHECK(IsQuietNaN(q2));
+  CHECK(IsQuietNaN(qa));
 
   // The input NaNs after passing through ProcessNaN.
   double s1_proc = rawbits_to_double(0x7ffd555511111111);
   double s2_proc = rawbits_to_double(0x7ffd555522222222);
   double sa_proc = rawbits_to_double(0x7ffd5555aaaaaaaa);
   double q1_proc = q1;
   double q2_proc = q2;
   double qa_proc = qa;
-  DCHECK(IsQuietNaN(s1_proc));
-  DCHECK(IsQuietNaN(s2_proc));
-  DCHECK(IsQuietNaN(sa_proc));
-  DCHECK(IsQuietNaN(q1_proc));
-  DCHECK(IsQuietNaN(q2_proc));
-  DCHECK(IsQuietNaN(qa_proc));
+  CHECK(IsQuietNaN(s1_proc));
+  CHECK(IsQuietNaN(s2_proc));
+  CHECK(IsQuietNaN(sa_proc));
+  CHECK(IsQuietNaN(q1_proc));
+  CHECK(IsQuietNaN(q2_proc));
+  CHECK(IsQuietNaN(qa_proc));
 
   // Negated NaNs as it would be done on ARMv8 hardware.
   double s1_proc_neg = rawbits_to_double(0xfffd555511111111);
   double sa_proc_neg = rawbits_to_double(0xfffd5555aaaaaaaa);
   double q1_proc_neg = rawbits_to_double(0xfffaaaaa11111111);
   double qa_proc_neg = rawbits_to_double(0xfffaaaaaaaaaaaaa);
-  DCHECK(IsQuietNaN(s1_proc_neg));
-  DCHECK(IsQuietNaN(sa_proc_neg));
-  DCHECK(IsQuietNaN(q1_proc_neg));
-  DCHECK(IsQuietNaN(qa_proc_neg));
+  CHECK(IsQuietNaN(s1_proc_neg));
+  CHECK(IsQuietNaN(sa_proc_neg));
+  CHECK(IsQuietNaN(q1_proc_neg));
+  CHECK(IsQuietNaN(qa_proc_neg));
 
   // Quiet NaNs are propagated.
   FmaddFmsubHelper(q1, 0, 0, q1_proc, q1_proc_neg, q1_proc_neg, q1_proc);
   FmaddFmsubHelper(0, q2, 0, q2_proc, q2_proc, q2_proc, q2_proc);
   FmaddFmsubHelper(0, 0, qa, qa_proc, qa_proc, qa_proc_neg, qa_proc_neg);
   FmaddFmsubHelper(q1, q2, 0, q1_proc, q1_proc_neg, q1_proc_neg, q1_proc);
   FmaddFmsubHelper(0, q2, qa, qa_proc, qa_proc, qa_proc_neg, qa_proc_neg);
   FmaddFmsubHelper(q1, 0, qa, qa_proc, qa_proc, qa_proc_neg, qa_proc_neg);
   FmaddFmsubHelper(q1, q2, qa, qa_proc, qa_proc, qa_proc_neg, qa_proc_neg);
 
@@ skipping 33 matching lines @@
 
 TEST(fmadd_fmsub_float_nans) {
   INIT_V8();
   // Make sure that NaN propagation works correctly.
   float s1 = rawbits_to_float(0x7f951111);
   float s2 = rawbits_to_float(0x7f952222);
   float sa = rawbits_to_float(0x7f95aaaa);
   float q1 = rawbits_to_float(0x7fea1111);
   float q2 = rawbits_to_float(0x7fea2222);
   float qa = rawbits_to_float(0x7feaaaaa);
-  DCHECK(IsSignallingNaN(s1));
-  DCHECK(IsSignallingNaN(s2));
-  DCHECK(IsSignallingNaN(sa));
-  DCHECK(IsQuietNaN(q1));
-  DCHECK(IsQuietNaN(q2));
-  DCHECK(IsQuietNaN(qa));
+  CHECK(IsSignallingNaN(s1));
+  CHECK(IsSignallingNaN(s2));
+  CHECK(IsSignallingNaN(sa));
+  CHECK(IsQuietNaN(q1));
+  CHECK(IsQuietNaN(q2));
+  CHECK(IsQuietNaN(qa));
 
   // The input NaNs after passing through ProcessNaN.
   float s1_proc = rawbits_to_float(0x7fd51111);
   float s2_proc = rawbits_to_float(0x7fd52222);
   float sa_proc = rawbits_to_float(0x7fd5aaaa);
   float q1_proc = q1;
   float q2_proc = q2;
   float qa_proc = qa;
-  DCHECK(IsQuietNaN(s1_proc));
-  DCHECK(IsQuietNaN(s2_proc));
-  DCHECK(IsQuietNaN(sa_proc));
-  DCHECK(IsQuietNaN(q1_proc));
-  DCHECK(IsQuietNaN(q2_proc));
-  DCHECK(IsQuietNaN(qa_proc));
+  CHECK(IsQuietNaN(s1_proc));
+  CHECK(IsQuietNaN(s2_proc));
+  CHECK(IsQuietNaN(sa_proc));
+  CHECK(IsQuietNaN(q1_proc));
+  CHECK(IsQuietNaN(q2_proc));
+  CHECK(IsQuietNaN(qa_proc));
 
   // Negated NaNs as it would be done on ARMv8 hardware.
   float s1_proc_neg = rawbits_to_float(0xffd51111);
   float sa_proc_neg = rawbits_to_float(0xffd5aaaa);
   float q1_proc_neg = rawbits_to_float(0xffea1111);
   float qa_proc_neg = rawbits_to_float(0xffeaaaaa);
-  DCHECK(IsQuietNaN(s1_proc_neg));
-  DCHECK(IsQuietNaN(sa_proc_neg));
-  DCHECK(IsQuietNaN(q1_proc_neg));
-  DCHECK(IsQuietNaN(qa_proc_neg));
+  CHECK(IsQuietNaN(s1_proc_neg));
+  CHECK(IsQuietNaN(sa_proc_neg));
+  CHECK(IsQuietNaN(q1_proc_neg));
+  CHECK(IsQuietNaN(qa_proc_neg));
 
   // Quiet NaNs are propagated.
   FmaddFmsubHelper(q1, 0, 0, q1_proc, q1_proc_neg, q1_proc_neg, q1_proc);
   FmaddFmsubHelper(0, q2, 0, q2_proc, q2_proc, q2_proc, q2_proc);
   FmaddFmsubHelper(0, 0, qa, qa_proc, qa_proc, qa_proc_neg, qa_proc_neg);
   FmaddFmsubHelper(q1, q2, 0, q1_proc, q1_proc_neg, q1_proc_neg, q1_proc);
   FmaddFmsubHelper(0, q2, qa, qa_proc, qa_proc, qa_proc_neg, qa_proc_neg);
   FmaddFmsubHelper(q1, 0, qa, qa_proc, qa_proc, qa_proc_neg, qa_proc_neg);
   FmaddFmsubHelper(q1, q2, qa, qa_proc, qa_proc, qa_proc_neg, qa_proc_neg);
 
@@ skipping 197 matching lines @@
 
 TEST(fmax_fmin_d) {
   INIT_V8();
   // Use non-standard NaNs to check that the payload bits are preserved.
   double snan = rawbits_to_double(0x7ff5555512345678);
   double qnan = rawbits_to_double(0x7ffaaaaa87654321);
 
   double snan_processed = rawbits_to_double(0x7ffd555512345678);
   double qnan_processed = qnan;
 
-  DCHECK(IsSignallingNaN(snan));
-  DCHECK(IsQuietNaN(qnan));
-  DCHECK(IsQuietNaN(snan_processed));
-  DCHECK(IsQuietNaN(qnan_processed));
+  CHECK(IsSignallingNaN(snan));
+  CHECK(IsQuietNaN(qnan));
+  CHECK(IsQuietNaN(snan_processed));
+  CHECK(IsQuietNaN(qnan_processed));
 
   // Bootstrap tests.
   FminFmaxDoubleHelper(0, 0, 0, 0, 0, 0);
   FminFmaxDoubleHelper(0, 1, 0, 1, 0, 1);
   FminFmaxDoubleHelper(kFP64PositiveInfinity, kFP64NegativeInfinity,
                        kFP64NegativeInfinity, kFP64PositiveInfinity,
                        kFP64NegativeInfinity, kFP64PositiveInfinity);
   FminFmaxDoubleHelper(snan, 0,
                        snan_processed, snan_processed,
                        snan_processed, snan_processed);
@@ skipping 61 matching lines @@
 
 TEST(fmax_fmin_s) {
   INIT_V8();
   // Use non-standard NaNs to check that the payload bits are preserved.
   float snan = rawbits_to_float(0x7f951234);
   float qnan = rawbits_to_float(0x7fea8765);
 
   float snan_processed = rawbits_to_float(0x7fd51234);
   float qnan_processed = qnan;
 
-  DCHECK(IsSignallingNaN(snan));
-  DCHECK(IsQuietNaN(qnan));
-  DCHECK(IsQuietNaN(snan_processed));
-  DCHECK(IsQuietNaN(qnan_processed));
+  CHECK(IsSignallingNaN(snan));
+  CHECK(IsQuietNaN(qnan));
+  CHECK(IsQuietNaN(snan_processed));
+  CHECK(IsQuietNaN(qnan_processed));
 
   // Bootstrap tests.
   FminFmaxFloatHelper(0, 0, 0, 0, 0, 0);
   FminFmaxFloatHelper(0, 1, 0, 1, 0, 1);
   FminFmaxFloatHelper(kFP32PositiveInfinity, kFP32NegativeInfinity,
                       kFP32NegativeInfinity, kFP32PositiveInfinity,
                       kFP32NegativeInfinity, kFP32PositiveInfinity);
   FminFmaxFloatHelper(snan, 0,
                       snan_processed, snan_processed,
                       snan_processed, snan_processed);
@@ skipping 951 matching lines @@
     {rawbits_to_double(0x7ff02468bfffffff), rawbits_to_float(0x7fc12345)},
     {rawbits_to_double(0x7ff000001fffffff), rawbits_to_float(0x7fc00000)},
   };
   int count = sizeof(test) / sizeof(test[0]);
 
   for (int i = 0; i < count; i++) {
     double in = test[i].in;
     float expected = test[i].expected;
 
     // We only expect positive input.
-    DCHECK(std::signbit(in) == 0);
-    DCHECK(std::signbit(expected) == 0);
+    CHECK(std::signbit(in) == 0);
+    CHECK(std::signbit(expected) == 0);
 
     SETUP();
     START();
 
     __ Fmov(d10, in);
     __ Fcvt(s20, d10);
 
     __ Fmov(d11, -in);
     __ Fcvt(s21, d11);
 
@@ skipping 1690 matching lines @@
   __ Claim(4);
 
   // Mix with other stack operations.
   //  After this section:
   //    x0-x3 should be unchanged.
   //    x6 should match x1[31:0]:x0[63:32]
   //    w7 should match x1[15:0]:x0[63:48]
   __ Poke(x1, 8);
   __ Poke(x0, 0);
   {
-    DCHECK(__ StackPointer().Is(csp));
+    CHECK(__ StackPointer().Is(csp));
     __ Mov(x4, __ StackPointer());
     __ SetStackPointer(x4);
 
     __ Poke(wzr, 0);    // Clobber the space we're about to drop.
     __ Drop(1, kWRegSize);
     __ Peek(x6, 0);
     __ Claim(1);
     __ Peek(w7, 10);
     __ Poke(x3, 28);
     __ Poke(xzr, 0);    // Clobber the space we're about to drop.
@@ skipping 76 matching lines @@
                                        allowed);
 
   // The literal base is chosen to have two useful properties:
   //  * When multiplied by small values (such as a register index), this value
   //    is clearly readable in the result.
   //  * The value is not formed from repeating fixed-size smaller values, so it
   //    can be used to detect endianness-related errors.
   uint64_t literal_base = 0x0100001000100101UL;
 
   {
-    DCHECK(__ StackPointer().Is(csp));
+    CHECK(__ StackPointer().Is(csp));
     __ Mov(jssp, __ StackPointer());
     __ SetStackPointer(jssp);
 
     int i;
 
     // Initialize the registers.
     for (i = 0; i < reg_count; i++) {
       // Always write into the X register, to ensure that the upper word is
       // properly ignored by Push when testing W registers.
       if (!x[i].IsZero()) {
         __ Mov(x[i], literal_base * i);
       }
     }
 
     // Claim memory first, as requested.
     __ Claim(claim, kByteSizeInBytes);
 
     switch (push_method) {
       case PushPopByFour:
         // Push high-numbered registers first (to the highest addresses).
         for (i = reg_count; i >= 4; i -= 4) {
           __ Push(r[i-1], r[i-2], r[i-3], r[i-4]);
         }
         // Finish off the leftovers.
         switch (i) {
           case 3:  __ Push(r[2], r[1], r[0]); break;
           case 2:  __ Push(r[1], r[0]);       break;
           case 1:  __ Push(r[0]);             break;
-          default: DCHECK(i == 0);            break;
+          default:
+            CHECK(i == 0);
+            break;
         }
         break;
       case PushPopRegList:
         __ PushSizeRegList(list, reg_size);
         break;
     }
 
     // Clobber all the registers, to ensure that they get repopulated by Pop.
     Clobber(&masm, list);
 
     switch (pop_method) {
       case PushPopByFour:
         // Pop low-numbered registers first (from the lowest addresses).
         for (i = 0; i <= (reg_count-4); i += 4) {
           __ Pop(r[i], r[i+1], r[i+2], r[i+3]);
         }
         // Finish off the leftovers.
         switch (reg_count - i) {
           case 3:  __ Pop(r[i], r[i+1], r[i+2]); break;
           case 2:  __ Pop(r[i], r[i+1]);         break;
           case 1:  __ Pop(r[i]);                 break;
-          default: DCHECK(i == reg_count);       break;
+          default:
+            CHECK(i == reg_count);
+            break;
         }
         break;
       case PushPopRegList:
         __ PopSizeRegList(list, reg_size);
         break;
     }
 
     // Drop memory to restore jssp.
     __ Drop(claim, kByteSizeInBytes);
 
@@ skipping 110 matching lines @@
   // The literal base is chosen to have two useful properties:
   //  * When multiplied (using an integer) by small values (such as a register
   //    index), this value is clearly readable in the result.
   //  * The value is not formed from repeating fixed-size smaller values, so it
   //    can be used to detect endianness-related errors.
   //  * It is never a floating-point NaN, and will therefore always compare
   //    equal to itself.
   uint64_t literal_base = 0x0100001000100101UL;
 
   {
-    DCHECK(__ StackPointer().Is(csp));
+    CHECK(__ StackPointer().Is(csp));
     __ Mov(jssp, __ StackPointer());
     __ SetStackPointer(jssp);
 
     int i;
 
     // Initialize the registers, using X registers to load the literal.
     __ Mov(x0, 0);
     __ Mov(x1, literal_base);
     for (i = 0; i < reg_count; i++) {
       // Always write into the D register, to ensure that the upper word is
@@ skipping 10 matching lines @@
       case PushPopByFour:
         // Push high-numbered registers first (to the highest addresses).
         for (i = reg_count; i >= 4; i -= 4) {
           __ Push(v[i-1], v[i-2], v[i-3], v[i-4]);
         }
         // Finish off the leftovers.
         switch (i) {
           case 3:  __ Push(v[2], v[1], v[0]); break;
           case 2:  __ Push(v[1], v[0]);       break;
           case 1:  __ Push(v[0]);             break;
-          default: DCHECK(i == 0);            break;
+          default:
+            CHECK(i == 0);
+            break;
         }
         break;
       case PushPopRegList:
         __ PushSizeRegList(list, reg_size, CPURegister::kFPRegister);
         break;
     }
 
     // Clobber all the registers, to ensure that they get repopulated by Pop.
     ClobberFP(&masm, list);
 
     switch (pop_method) {
       case PushPopByFour:
         // Pop low-numbered registers first (from the lowest addresses).
         for (i = 0; i <= (reg_count-4); i += 4) {
           __ Pop(v[i], v[i+1], v[i+2], v[i+3]);
         }
         // Finish off the leftovers.
         switch (reg_count - i) {
           case 3:  __ Pop(v[i], v[i+1], v[i+2]); break;
           case 2:  __ Pop(v[i], v[i+1]);         break;
           case 1:  __ Pop(v[i]);                 break;
-          default: DCHECK(i == reg_count);       break;
+          default:
+            CHECK(i == reg_count);
+            break;
         }
         break;
       case PushPopRegList:
         __ PopSizeRegList(list, reg_size, CPURegister::kFPRegister);
         break;
     }
 
     // Drop memory to restore jssp.
     __ Drop(claim, kByteSizeInBytes);
 
@@ skipping 103 matching lines @@
 
   // The literal base is chosen to have two useful properties:
   //  * When multiplied by small values (such as a register index), this value
   //    is clearly readable in the result.
   //  * The value is not formed from repeating fixed-size smaller values, so it
   //    can be used to detect endianness-related errors.
   uint64_t literal_base = 0x0100001000100101UL;
 
   START();
   {
-    DCHECK(__ StackPointer().Is(csp));
+    CHECK(__ StackPointer().Is(csp));
     __ Mov(jssp, __ StackPointer());
     __ SetStackPointer(jssp);
 
     // Claim memory first, as requested.
     __ Claim(claim, kByteSizeInBytes);
 
     __ Mov(x[3], literal_base * 3);
     __ Mov(x[2], literal_base * 2);
     __ Mov(x[1], literal_base * 1);
     __ Mov(x[0], literal_base * 0);
@@ skipping 84 matching lines @@
   //    is clearly readable in the result.
   //  * The value is not formed from repeating fixed-size smaller values, so it
   //    can be used to detect endianness-related errors.
   static uint64_t const literal_base = 0x0100001000100101UL;
   static uint64_t const literal_base_hi = literal_base >> 32;
   static uint64_t const literal_base_lo = literal_base & 0xffffffff;
   static uint64_t const literal_base_w = literal_base & 0xffffffff;
 
   START();
   {
-    DCHECK(__ StackPointer().Is(csp));
+    CHECK(__ StackPointer().Is(csp));
     __ Mov(jssp, __ StackPointer());
     __ SetStackPointer(jssp);
 
     // Initialize the registers.
     for (int i = 0; i < reg_count; i++) {
       // Always write into the X register, to ensure that the upper word is
       // properly ignored by Push when testing W registers.
       if (!x[i].IsZero()) {
         __ Mov(x[i], literal_base * i);
       }
@@ skipping 27 matching lines @@
     // where i is the register number.
     // Registers are popped starting with the higher numbers one-by-one,
     // alternating between x and w registers, but only popping one at a time.
     //
     // This pattern provides a wide variety of alignment effects and overlaps.
 
     // ---- Push ----
 
     int active_w_slots = 0;
     for (int i = 0; active_w_slots < requested_w_slots; i++) {
-      DCHECK(i < reg_count);
+      CHECK(i < reg_count);
       // In order to test various arguments to PushMultipleTimes, and to try to
       // exercise different alignment and overlap effects, we push each
       // register a different number of times.
       int times = i % 4 + 1;
       if (i & 1) {
         // Push odd-numbered registers as W registers.
         if (i & 2) {
           __ PushMultipleTimes(w[i], times);
         } else {
           // Use a register to specify the count.
@@ skipping 52 matching lines @@
     for (int i = reg_count-1; i >= 0; i--) {
       if (next_is_64) {
         __ Pop(x[i]);
         active_w_slots -= 2;
       } else {
         __ Pop(w[i]);
         active_w_slots -= 1;
       }
       next_is_64 = !next_is_64;
     }
-    DCHECK(active_w_slots == 0);
+    CHECK(active_w_slots == 0);
 
     // Drop memory to restore jssp.
     __ Drop(claim, kByteSizeInBytes);
 
     __ Mov(csp, __ StackPointer());
     __ SetStackPointer(csp);
   }
 
   END();
 
@@ skipping 15 matching lines @@
     }
 
     // Always use CHECK_EQUAL_64, even when testing W registers, so we can
     // test that the upper word was properly cleared by Pop.
     if (x[i].IsZero()) {
       CHECK_EQUAL_64(0, x[i]);
     } else {
       CHECK_EQUAL_64(expected, x[i]);
     }
   }
-  DCHECK(slot == requested_w_slots);
+  CHECK(slot == requested_w_slots);
 
   TEARDOWN();
 }
 
 
 TEST(push_pop_jssp_wx_overlap) {
   INIT_V8();
   for (int claim = 0; claim <= 8; claim++) {
     for (int count = 1; count <= 8; count++) {
       PushPopJsspWXOverlapHelper(count, claim);
       PushPopJsspWXOverlapHelper(count, claim);
       PushPopJsspWXOverlapHelper(count, claim);
       PushPopJsspWXOverlapHelper(count, claim);
     }
     // Test with the maximum number of registers.
     PushPopJsspWXOverlapHelper(kPushPopJsspMaxRegCount, claim);
     PushPopJsspWXOverlapHelper(kPushPopJsspMaxRegCount, claim);
     PushPopJsspWXOverlapHelper(kPushPopJsspMaxRegCount, claim);
     PushPopJsspWXOverlapHelper(kPushPopJsspMaxRegCount, claim);
   }
 }
 
 
 TEST(push_pop_csp) {
   INIT_V8();
   SETUP();
 
   START();
 
-  DCHECK(csp.Is(__ StackPointer()));
+  CHECK(csp.Is(__ StackPointer()));
 
   __ Mov(x3, 0x3333333333333333UL);
   __ Mov(x2, 0x2222222222222222UL);
   __ Mov(x1, 0x1111111111111111UL);
   __ Mov(x0, 0x0000000000000000UL);
   __ Claim(2);
   __ PushXRegList(x0.Bit() | x1.Bit() | x2.Bit() | x3.Bit());
   __ Push(x3, x2);
   __ PopXRegList(x0.Bit() | x1.Bit() | x2.Bit() | x3.Bit());
   __ Push(x2, x1, x3, x0);
@@ skipping 68 matching lines @@
   TEARDOWN();
 }
 
 
 TEST(push_queued) {
   INIT_V8();
   SETUP();
 
   START();
 
-  DCHECK(__ StackPointer().Is(csp));
+  CHECK(__ StackPointer().Is(csp));
   __ Mov(jssp, __ StackPointer());
   __ SetStackPointer(jssp);
 
   MacroAssembler::PushPopQueue queue(&masm);
 
   // Queue up registers.
   queue.Queue(x0);
   queue.Queue(x1);
   queue.Queue(x2);
   queue.Queue(x3);
@@ skipping 54 matching lines @@
   TEARDOWN();
 }
 
 
 TEST(pop_queued) {
   INIT_V8();
   SETUP();
 
   START();
 
-  DCHECK(__ StackPointer().Is(csp));
+  CHECK(__ StackPointer().Is(csp));
   __ Mov(jssp, __ StackPointer());
   __ SetStackPointer(jssp);
 
   MacroAssembler::PushPopQueue queue(&masm);
 
   __ Mov(x0, 0x1234000000000000);
   __ Mov(x1, 0x1234000100010001);
   __ Mov(x2, 0x1234000200020002);
   __ Mov(x3, 0x1234000300030003);
   __ Mov(w4, 0x12340004);
@@ skipping 600 matching lines @@
   __ Printf("Test %%s: %s\n", x2);
   __ Printf("w3(uint32): %" PRIu32 "\nw4(int32): %" PRId32 "\n"
             "x5(uint64): %" PRIu64 "\nx6(int64): %" PRId64 "\n",
             w3, w4, x5, x6);
   __ Printf("%%f: %f\n%%g: %g\n%%e: %e\n%%E: %E\n", s1, s2, d3, d4);
   __ Printf("0x%" PRIx32 ", 0x%" PRIx64 "\n", w28, x28);
   __ Printf("%g\n", d10);
   __ Printf("%%%%%s%%%c%%\n", x2, w13);
 
   // Print the stack pointer (csp).
-  DCHECK(csp.Is(__ StackPointer()));
+  CHECK(csp.Is(__ StackPointer()));
   __ Printf("StackPointer(csp): 0x%016" PRIx64 ", 0x%08" PRIx32 "\n",
             __ StackPointer(), __ StackPointer().W());
 
   // Test with a different stack pointer.
   const Register old_stack_pointer = __ StackPointer();
   __ Mov(x29, old_stack_pointer);
   __ SetStackPointer(x29);
   // Print the stack pointer (not csp).
   __ Printf("StackPointer(not csp): 0x%016" PRIx64 ", 0x%08" PRIx32 "\n",
             __ StackPointer(), __ StackPointer().W());
@@ skipping 232 matching lines @@
 
   TEARDOWN();
 }
 
 
 TEST(process_nan_double) {
   INIT_V8();
   // Make sure that NaN propagation works correctly.
   double sn = rawbits_to_double(0x7ff5555511111111);
   double qn = rawbits_to_double(0x7ffaaaaa11111111);
-  DCHECK(IsSignallingNaN(sn));
-  DCHECK(IsQuietNaN(qn));
+  CHECK(IsSignallingNaN(sn));
+  CHECK(IsQuietNaN(qn));
 
   // The input NaNs after passing through ProcessNaN.
   double sn_proc = rawbits_to_double(0x7ffd555511111111);
   double qn_proc = qn;
-  DCHECK(IsQuietNaN(sn_proc));
-  DCHECK(IsQuietNaN(qn_proc));
+  CHECK(IsQuietNaN(sn_proc));
+  CHECK(IsQuietNaN(qn_proc));
 
   SETUP();
   START();
 
   // Execute a number of instructions which all use ProcessNaN, and check that
   // they all handle the NaN correctly.
   __ Fmov(d0, sn);
   __ Fmov(d10, qn);
 
   // Operations that always propagate NaNs unchanged, even signalling NaNs.
@@ skipping 48 matching lines @@
 
   TEARDOWN();
 }
 
 
 TEST(process_nan_float) {
   INIT_V8();
   // Make sure that NaN propagation works correctly.
   float sn = rawbits_to_float(0x7f951111);
   float qn = rawbits_to_float(0x7fea1111);
-  DCHECK(IsSignallingNaN(sn));
-  DCHECK(IsQuietNaN(qn));
+  CHECK(IsSignallingNaN(sn));
+  CHECK(IsQuietNaN(qn));
 
   // The input NaNs after passing through ProcessNaN.
   float sn_proc = rawbits_to_float(0x7fd51111);
   float qn_proc = qn;
-  DCHECK(IsQuietNaN(sn_proc));
-  DCHECK(IsQuietNaN(qn_proc));
+  CHECK(IsQuietNaN(sn_proc));
+  CHECK(IsQuietNaN(qn_proc));
 
   SETUP();
   START();
 
   // Execute a number of instructions which all use ProcessNaN, and check that
   // they all handle the NaN correctly.
   __ Fmov(s0, sn);
   __ Fmov(s10, qn);
 
   // Operations that always propagate NaNs unchanged, even signalling NaNs.
@@ skipping 44 matching lines @@
   CHECK_EQUAL_FP32(qn_proc, s14);
   CHECK_EQUAL_FP32(qn_proc, s15);
   CHECK_EQUAL_FP32(qn_proc, s16);
   CHECK_EQUAL_FP32(qn_proc, s17);
 
   TEARDOWN();
 }
 
 
 static void ProcessNaNsHelper(double n, double m, double expected) {
-  DCHECK(std::isnan(n) || std::isnan(m));
-  DCHECK(std::isnan(expected));
+  CHECK(std::isnan(n) || std::isnan(m));
+  CHECK(std::isnan(expected));
 
   SETUP();
   START();
 
   // Execute a number of instructions which all use ProcessNaNs, and check that
   // they all propagate NaNs correctly.
   __ Fmov(d0, n);
   __ Fmov(d1, m);
 
   __ Fadd(d2, d0, d1);
@@ skipping 17 matching lines @@
 }
 
 
 TEST(process_nans_double) {
   INIT_V8();
   // Make sure that NaN propagation works correctly.
   double sn = rawbits_to_double(0x7ff5555511111111);
   double sm = rawbits_to_double(0x7ff5555522222222);
   double qn = rawbits_to_double(0x7ffaaaaa11111111);
   double qm = rawbits_to_double(0x7ffaaaaa22222222);
-  DCHECK(IsSignallingNaN(sn));
-  DCHECK(IsSignallingNaN(sm));
-  DCHECK(IsQuietNaN(qn));
-  DCHECK(IsQuietNaN(qm));
+  CHECK(IsSignallingNaN(sn));
+  CHECK(IsSignallingNaN(sm));
+  CHECK(IsQuietNaN(qn));
+  CHECK(IsQuietNaN(qm));
 
   // The input NaNs after passing through ProcessNaN.
   double sn_proc = rawbits_to_double(0x7ffd555511111111);
   double sm_proc = rawbits_to_double(0x7ffd555522222222);
   double qn_proc = qn;
   double qm_proc = qm;
-  DCHECK(IsQuietNaN(sn_proc));
-  DCHECK(IsQuietNaN(sm_proc));
-  DCHECK(IsQuietNaN(qn_proc));
-  DCHECK(IsQuietNaN(qm_proc));
+  CHECK(IsQuietNaN(sn_proc));
+  CHECK(IsQuietNaN(sm_proc));
+  CHECK(IsQuietNaN(qn_proc));
+  CHECK(IsQuietNaN(qm_proc));
 
   // Quiet NaNs are propagated.
   ProcessNaNsHelper(qn, 0, qn_proc);
   ProcessNaNsHelper(0, qm, qm_proc);
   ProcessNaNsHelper(qn, qm, qn_proc);
 
   // Signalling NaNs are propagated, and made quiet.
   ProcessNaNsHelper(sn, 0, sn_proc);
   ProcessNaNsHelper(0, sm, sm_proc);
   ProcessNaNsHelper(sn, sm, sn_proc);
 
   // Signalling NaNs take precedence over quiet NaNs.
   ProcessNaNsHelper(sn, qm, sn_proc);
   ProcessNaNsHelper(qn, sm, sm_proc);
   ProcessNaNsHelper(sn, sm, sn_proc);
 }
 
 
 static void ProcessNaNsHelper(float n, float m, float expected) {
-  DCHECK(std::isnan(n) || std::isnan(m));
-  DCHECK(std::isnan(expected));
+  CHECK(std::isnan(n) || std::isnan(m));
+  CHECK(std::isnan(expected));
 
   SETUP();
   START();
 
   // Execute a number of instructions which all use ProcessNaNs, and check that
   // they all propagate NaNs correctly.
   __ Fmov(s0, n);
   __ Fmov(s1, m);
 
   __ Fadd(s2, s0, s1);
@@ skipping 17 matching lines @@
 }
 
 
 TEST(process_nans_float) {
   INIT_V8();
   // Make sure that NaN propagation works correctly.
   float sn = rawbits_to_float(0x7f951111);
   float sm = rawbits_to_float(0x7f952222);
   float qn = rawbits_to_float(0x7fea1111);
   float qm = rawbits_to_float(0x7fea2222);
-  DCHECK(IsSignallingNaN(sn));
-  DCHECK(IsSignallingNaN(sm));
-  DCHECK(IsQuietNaN(qn));
-  DCHECK(IsQuietNaN(qm));
+  CHECK(IsSignallingNaN(sn));
+  CHECK(IsSignallingNaN(sm));
+  CHECK(IsQuietNaN(qn));
+  CHECK(IsQuietNaN(qm));
 
   // The input NaNs after passing through ProcessNaN.
   float sn_proc = rawbits_to_float(0x7fd51111);
   float sm_proc = rawbits_to_float(0x7fd52222);
   float qn_proc = qn;
   float qm_proc = qm;
-  DCHECK(IsQuietNaN(sn_proc));
-  DCHECK(IsQuietNaN(sm_proc));
-  DCHECK(IsQuietNaN(qn_proc));
-  DCHECK(IsQuietNaN(qm_proc));
+  CHECK(IsQuietNaN(sn_proc));
+  CHECK(IsQuietNaN(sm_proc));
+  CHECK(IsQuietNaN(qn_proc));
+  CHECK(IsQuietNaN(qm_proc));
 
   // Quiet NaNs are propagated.
   ProcessNaNsHelper(qn, 0, qn_proc);
   ProcessNaNsHelper(0, qm, qm_proc);
   ProcessNaNsHelper(qn, qm, qn_proc);
 
   // Signalling NaNs are propagated, and made quiet.
   ProcessNaNsHelper(sn, 0, sn_proc);
   ProcessNaNsHelper(0, sm, sm_proc);
   ProcessNaNsHelper(sn, sm, sn_proc);
 
   // Signalling NaNs take precedence over quiet NaNs.
   ProcessNaNsHelper(sn, qm, sn_proc);
   ProcessNaNsHelper(qn, sm, sm_proc);
   ProcessNaNsHelper(sn, sm, sn_proc);
 }
 
 
 static void DefaultNaNHelper(float n, float m, float a) {
-  DCHECK(std::isnan(n) || std::isnan(m) || std::isnan(a));
+  CHECK(std::isnan(n) || std::isnan(m) || std::isnan(a));
 
   bool test_1op = std::isnan(n);
   bool test_2op = std::isnan(n) || std::isnan(m);
 
   SETUP();
   START();
 
   // Enable Default-NaN mode in the FPCR.
   __ Mrs(x0, FPCR);
   __ Orr(x1, x0, DN_mask);
@@ skipping 72 matching lines @@
 
 
 TEST(default_nan_float) {
   INIT_V8();
   float sn = rawbits_to_float(0x7f951111);
   float sm = rawbits_to_float(0x7f952222);
   float sa = rawbits_to_float(0x7f95aaaa);
   float qn = rawbits_to_float(0x7fea1111);
   float qm = rawbits_to_float(0x7fea2222);
   float qa = rawbits_to_float(0x7feaaaaa);
-  DCHECK(IsSignallingNaN(sn));
-  DCHECK(IsSignallingNaN(sm));
-  DCHECK(IsSignallingNaN(sa));
-  DCHECK(IsQuietNaN(qn));
-  DCHECK(IsQuietNaN(qm));
-  DCHECK(IsQuietNaN(qa));
+  CHECK(IsSignallingNaN(sn));
+  CHECK(IsSignallingNaN(sm));
+  CHECK(IsSignallingNaN(sa));
+  CHECK(IsQuietNaN(qn));
+  CHECK(IsQuietNaN(qm));
+  CHECK(IsQuietNaN(qa));
 
   //   - Signalling NaNs
   DefaultNaNHelper(sn, 0.0f, 0.0f);
   DefaultNaNHelper(0.0f, sm, 0.0f);
   DefaultNaNHelper(0.0f, 0.0f, sa);
   DefaultNaNHelper(sn, sm, 0.0f);
   DefaultNaNHelper(0.0f, sm, sa);
   DefaultNaNHelper(sn, 0.0f, sa);
   DefaultNaNHelper(sn, sm, sa);
   //   - Quiet NaNs
   DefaultNaNHelper(qn, 0.0f, 0.0f);
   DefaultNaNHelper(0.0f, qm, 0.0f);
   DefaultNaNHelper(0.0f, 0.0f, qa);
   DefaultNaNHelper(qn, qm, 0.0f);
   DefaultNaNHelper(0.0f, qm, qa);
   DefaultNaNHelper(qn, 0.0f, qa);
   DefaultNaNHelper(qn, qm, qa);
   //   - Mixed NaNs
   DefaultNaNHelper(qn, sm, sa);
   DefaultNaNHelper(sn, qm, sa);
   DefaultNaNHelper(sn, sm, qa);
   DefaultNaNHelper(qn, qm, sa);
   DefaultNaNHelper(sn, qm, qa);
   DefaultNaNHelper(qn, sm, qa);
   DefaultNaNHelper(qn, qm, qa);
 }
 
 
 static void DefaultNaNHelper(double n, double m, double a) {
-  DCHECK(std::isnan(n) || std::isnan(m) || std::isnan(a));
+  CHECK(std::isnan(n) || std::isnan(m) || std::isnan(a));
 
   bool test_1op = std::isnan(n);
   bool test_2op = std::isnan(n) || std::isnan(m);
 
   SETUP();
   START();
 
   // Enable Default-NaN mode in the FPCR.
   __ Mrs(x0, FPCR);
   __ Orr(x1, x0, DN_mask);
@@ skipping 72 matching lines @@
 
 
 TEST(default_nan_double) {
   INIT_V8();
   double sn = rawbits_to_double(0x7ff5555511111111);
   double sm = rawbits_to_double(0x7ff5555522222222);
   double sa = rawbits_to_double(0x7ff55555aaaaaaaa);
   double qn = rawbits_to_double(0x7ffaaaaa11111111);
   double qm = rawbits_to_double(0x7ffaaaaa22222222);
   double qa = rawbits_to_double(0x7ffaaaaaaaaaaaaa);
-  DCHECK(IsSignallingNaN(sn));
-  DCHECK(IsSignallingNaN(sm));
-  DCHECK(IsSignallingNaN(sa));
-  DCHECK(IsQuietNaN(qn));
-  DCHECK(IsQuietNaN(qm));
-  DCHECK(IsQuietNaN(qa));
+  CHECK(IsSignallingNaN(sn));
+  CHECK(IsSignallingNaN(sm));
+  CHECK(IsSignallingNaN(sa));
+  CHECK(IsQuietNaN(qn));
+  CHECK(IsQuietNaN(qm));
+  CHECK(IsQuietNaN(qa));
 
   //   - Signalling NaNs
   DefaultNaNHelper(sn, 0.0, 0.0);
   DefaultNaNHelper(0.0, sm, 0.0);
   DefaultNaNHelper(0.0, 0.0, sa);
   DefaultNaNHelper(sn, sm, 0.0);
   DefaultNaNHelper(0.0, sm, sa);
   DefaultNaNHelper(sn, 0.0, sa);
   DefaultNaNHelper(sn, sm, sa);
   //   - Quiet NaNs
@@ skipping 217 matching lines @@
   CodeDesc desc;
   masm.GetCode(&desc);
   Handle<Code> code = isolate->factory()->NewCode(desc, 0, masm.CodeObject());
 
   unsigned pool_count = 0;
   int pool_mask = RelocInfo::ModeMask(RelocInfo::CONST_POOL) |
                   RelocInfo::ModeMask(RelocInfo::VENEER_POOL);
   for (RelocIterator it(*code, pool_mask); !it.done(); it.next()) {
     RelocInfo* info = it.rinfo();
     if (RelocInfo::IsConstPool(info->rmode())) {
-      DCHECK(info->data() == constant_pool_size);
+      CHECK(info->data() == constant_pool_size);
       ++pool_count;
     }
     if (RelocInfo::IsVeneerPool(info->rmode())) {
-      DCHECK(info->data() == veneer_pool_size);
+      CHECK(info->data() == veneer_pool_size);
       ++pool_count;
     }
   }
 
-  DCHECK(pool_count == 2);
+  CHECK(pool_count == 2);
 
   TEARDOWN();
 }
 
 
 TEST(jump_tables_forward) {
   // Test jump tables with forward jumps.
   const int kNumCases = 512;
 
   INIT_V8();
@@ skipping 153 matching lines @@
   __ Mov(x0, 1);
 
   END();
 
   RUN();
 
   CHECK_EQUAL_64(0x1, x0);
 
   TEARDOWN();
 }