OLD | NEW |
1 //===- subzero/src/IceTargetLoweringX8664Traits.h - x86-64 traits -*- C++ -*-=// | 1 //===- subzero/src/IceTargetLoweringX8664Traits.h - x86-64 traits -*- C++ -*-=// |
2 // | 2 // |
3 // The Subzero Code Generator | 3 // The Subzero Code Generator |
4 // | 4 // |
5 // This file is distributed under the University of Illinois Open Source | 5 // This file is distributed under the University of Illinois Open Source |
6 // License. See LICENSE.TXT for details. | 6 // License. See LICENSE.TXT for details. |
7 // | 7 // |
8 //===----------------------------------------------------------------------===// | 8 //===----------------------------------------------------------------------===// |
9 /// | 9 /// |
10 /// \file | 10 /// \file |
(...skipping 54 matching lines...) Expand 10 before | Expand all | Expand 10 after Loading... |
65 using ByteRegister = ::Ice::RegX8664::ByteRegister; | 65 using ByteRegister = ::Ice::RegX8664::ByteRegister; |
66 using XmmRegister = ::Ice::RegX8664::XmmRegister; | 66 using XmmRegister = ::Ice::RegX8664::XmmRegister; |
67 | 67 |
68 using Cond = ::Ice::CondX8664; | 68 using Cond = ::Ice::CondX8664; |
69 | 69 |
70 using RegisterSet = ::Ice::RegX8664; | 70 using RegisterSet = ::Ice::RegX8664; |
71 static const SizeT StackPtr = RegX8664::Reg_rsp; | 71 static const SizeT StackPtr = RegX8664::Reg_rsp; |
72 static const SizeT FramePtr = RegX8664::Reg_rbp; | 72 static const SizeT FramePtr = RegX8664::Reg_rbp; |
73 static const GPRRegister Encoded_Reg_Accumulator = RegX8664::Encoded_Reg_eax; | 73 static const GPRRegister Encoded_Reg_Accumulator = RegX8664::Encoded_Reg_eax; |
74 static const GPRRegister Encoded_Reg_Counter = RegX8664::Encoded_Reg_ecx; | 74 static const GPRRegister Encoded_Reg_Counter = RegX8664::Encoded_Reg_ecx; |
75 static const FixupKind PcRelFixup = llvm::ELF::R_X86_64_PC32; | 75 static constexpr FixupKind FK_PcRel = llvm::ELF::R_X86_64_PC32; |
76 static const FixupKind RelFixup = llvm::ELF::R_X86_64_32; | 76 static constexpr FixupKind FK_Abs = llvm::ELF::R_X86_64_32; |
| 77 static constexpr FixupKind FK_Gotoff = llvm::ELF::R_X86_64_GOTOFF64; |
| 78 static constexpr FixupKind FK_GotPC = llvm::ELF::R_X86_64_GOTPC32; |
77 | 79 |
78 class Operand { | 80 class Operand { |
79 public: | 81 public: |
80 enum RexBits { | 82 enum RexBits { |
81 RexNone = 0x00, | 83 RexNone = 0x00, |
82 RexBase = 0x40, | 84 RexBase = 0x40, |
83 RexW = RexBase | (1 << 3), | 85 RexW = RexBase | (1 << 3), |
84 RexR = RexBase | (1 << 2), | 86 RexR = RexBase | (1 << 2), |
85 RexX = RexBase | (1 << 1), | 87 RexX = RexBase | (1 << 1), |
86 RexB = RexBase | (1 << 0), | 88 RexB = RexBase | (1 << 0), |
(...skipping 177 matching lines...) Expand 10 before | Expand all | Expand 10 after Loading... |
264 SetSIB(Scale, RegX8664::Encoded_Reg_esp, RegX8664::Encoded_Reg_ebp); | 266 SetSIB(Scale, RegX8664::Encoded_Reg_esp, RegX8664::Encoded_Reg_ebp); |
265 // Use the Offset in the displacement for now. If we decide to process | 267 // Use the Offset in the displacement for now. If we decide to process |
266 // fixups later, we'll need to patch up the emitted displacement. | 268 // fixups later, we'll need to patch up the emitted displacement. |
267 SetDisp32(Offset); | 269 SetDisp32(Offset); |
268 if (Fixup) | 270 if (Fixup) |
269 SetFixup(Fixup); | 271 SetFixup(Fixup); |
270 } | 272 } |
271 | 273 |
272 static Address ofConstPool(Assembler *Asm, const Constant *Imm) { | 274 static Address ofConstPool(Assembler *Asm, const Constant *Imm) { |
273 // TODO(jpp): ??? | 275 // TODO(jpp): ??? |
274 AssemblerFixup *Fixup = Asm->createFixup(RelFixup, Imm); | 276 AssemblerFixup *Fixup = Asm->createFixup(FK_Abs, Imm); |
275 const RelocOffsetT Offset = 4; | 277 const RelocOffsetT Offset = 4; |
276 return Address(Offset, Fixup); | 278 return Address(Offset, Fixup); |
277 } | 279 } |
278 }; | 280 }; |
279 | 281 |
280 //---------------------------------------------------------------------------- | 282 //---------------------------------------------------------------------------- |
281 // __ ______ __ __ ______ ______ __ __ __ ______ | 283 // __ ______ __ __ ______ ______ __ __ __ ______ |
282 // /\ \ /\ __ \/\ \ _ \ \/\ ___\/\ == \/\ \/\ "-.\ \/\ ___\ | 284 // /\ \ /\ __ \/\ \ _ \ \/\ ___\/\ == \/\ \/\ "-.\ \/\ ___\ |
283 // \ \ \___\ \ \/\ \ \ \/ ".\ \ \ __\\ \ __<\ \ \ \ \-. \ \ \__ \ | 285 // \ \ \___\ \ \/\ \ \ \/ ".\ \ \ __\\ \ __<\ \ \ \ \-. \ \ \__ \ |
284 // \ \_____\ \_____\ \__/".~\_\ \_____\ \_\ \_\ \_\ \_\\"\_\ \_____\ | 286 // \ \_____\ \_____\ \__/".~\_\ \_____\ \_\ \_\ \_\ \_\\"\_\ \_____\ |
(...skipping 547 matching lines...) Expand 10 before | Expand all | Expand 10 after Loading... |
832 class X86OperandMem : public X86Operand { | 834 class X86OperandMem : public X86Operand { |
833 X86OperandMem() = delete; | 835 X86OperandMem() = delete; |
834 X86OperandMem(const X86OperandMem &) = delete; | 836 X86OperandMem(const X86OperandMem &) = delete; |
835 X86OperandMem &operator=(const X86OperandMem &) = delete; | 837 X86OperandMem &operator=(const X86OperandMem &) = delete; |
836 | 838 |
837 public: | 839 public: |
838 enum SegmentRegisters { DefaultSegment = -1, SegReg_NUM }; | 840 enum SegmentRegisters { DefaultSegment = -1, SegReg_NUM }; |
839 static X86OperandMem * | 841 static X86OperandMem * |
840 create(Cfg *Func, Type Ty, Variable *Base, Constant *Offset, | 842 create(Cfg *Func, Type Ty, Variable *Base, Constant *Offset, |
841 Variable *Index = nullptr, uint16_t Shift = 0, | 843 Variable *Index = nullptr, uint16_t Shift = 0, |
842 SegmentRegisters SegmentRegister = DefaultSegment) { | 844 SegmentRegisters SegmentRegister = DefaultSegment, |
| 845 bool IsPIC = false) { |
843 assert(SegmentRegister == DefaultSegment); | 846 assert(SegmentRegister == DefaultSegment); |
844 (void)SegmentRegister; | 847 (void)SegmentRegister; |
845 return new (Func->allocate<X86OperandMem>()) | 848 return new (Func->allocate<X86OperandMem>()) |
846 X86OperandMem(Func, Ty, Base, Offset, Index, Shift); | 849 X86OperandMem(Func, Ty, Base, Offset, Index, Shift, IsPIC); |
847 } | 850 } |
848 Variable *getBase() const { return Base; } | 851 Variable *getBase() const { return Base; } |
849 Constant *getOffset() const { return Offset; } | 852 Constant *getOffset() const { return Offset; } |
850 Variable *getIndex() const { return Index; } | 853 Variable *getIndex() const { return Index; } |
851 uint16_t getShift() const { return Shift; } | 854 uint16_t getShift() const { return Shift; } |
852 SegmentRegisters getSegmentRegister() const { return DefaultSegment; } | 855 SegmentRegisters getSegmentRegister() const { return DefaultSegment; } |
853 void emitSegmentOverride(Assembler *) const {} | 856 void emitSegmentOverride(Assembler *) const {} |
| 857 void setIsPIC() { IsPIC = true; } |
| 858 bool getIsPIC() const { return IsPIC; } |
854 Address toAsmAddress(Assembler *Asm, | 859 Address toAsmAddress(Assembler *Asm, |
855 const Ice::TargetLowering *Target) const; | 860 const Ice::TargetLowering *Target) const; |
856 | 861 |
857 void emit(const Cfg *Func) const override; | 862 void emit(const Cfg *Func) const override; |
858 using X86Operand::dump; | 863 using X86Operand::dump; |
859 void dump(const Cfg *Func, Ostream &Str) const override; | 864 void dump(const Cfg *Func, Ostream &Str) const override; |
860 | 865 |
861 static bool classof(const Operand *Operand) { | 866 static bool classof(const Operand *Operand) { |
862 return Operand->getKind() == static_cast<OperandKind>(kMem); | 867 return Operand->getKind() == static_cast<OperandKind>(kMem); |
863 } | 868 } |
864 | 869 |
865 void setRandomized(bool R) { Randomized = R; } | 870 void setRandomized(bool R) { Randomized = R; } |
866 | 871 |
867 bool getRandomized() const { return Randomized; } | 872 bool getRandomized() const { return Randomized; } |
868 | 873 |
869 private: | 874 private: |
870 X86OperandMem(Cfg *Func, Type Ty, Variable *Base, Constant *Offset, | 875 X86OperandMem(Cfg *Func, Type Ty, Variable *Base, Constant *Offset, |
871 Variable *Index, uint16_t Shift); | 876 Variable *Index, uint16_t Shift, bool IsPIC); |
872 | 877 |
873 Variable *Base; | 878 Variable *Base; |
874 Constant *Offset; | 879 Constant *Offset; |
875 Variable *Index; | 880 Variable *Index; |
876 uint16_t Shift; | 881 uint16_t Shift; |
| 882 bool IsPIC; |
877 /// A flag to show if this memory operand is a randomized one. Randomized | 883 /// A flag to show if this memory operand is a randomized one. Randomized |
878 /// memory operands are generated in | 884 /// memory operands are generated in |
879 /// TargetX86Base::randomizeOrPoolImmediate() | 885 /// TargetX86Base::randomizeOrPoolImmediate() |
880 bool Randomized = false; | 886 bool Randomized = false; |
881 }; | 887 }; |
882 | 888 |
883 /// VariableSplit is a way to treat an f64 memory location as a pair of i32 | 889 /// VariableSplit is a way to treat an f64 memory location as a pair of i32 |
884 /// locations (Low and High). This is needed for some cases of the Bitcast | 890 /// locations (Low and High). This is needed for some cases of the Bitcast |
885 /// instruction. Since it's not possible for integer registers to access the | 891 /// instruction. Since it's not possible for integer registers to access the |
886 /// XMM registers and vice versa, the lowering forces the f64 to be spilled to | 892 /// XMM registers and vice versa, the lowering forces the f64 to be spilled to |
(...skipping 86 matching lines...) Expand 10 before | Expand all | Expand 10 after Loading... |
973 const char *FldString; // s, l, or <blank> | 979 const char *FldString; // s, l, or <blank> |
974 } TypeAttributes[]; | 980 } TypeAttributes[]; |
975 }; | 981 }; |
976 | 982 |
977 using Traits = ::Ice::X8664::TargetX8664Traits; | 983 using Traits = ::Ice::X8664::TargetX8664Traits; |
978 } // end of namespace X8664 | 984 } // end of namespace X8664 |
979 | 985 |
980 } // end of namespace Ice | 986 } // end of namespace Ice |
981 | 987 |
982 #endif // SUBZERO_SRC_ICETARGETLOWERINGX8664TRAITS_H | 988 #endif // SUBZERO_SRC_ICETARGETLOWERINGX8664TRAITS_H |
OLD | NEW |