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1 //===- subzero/src/IceTargetLoweringX8632Traits.h - x86-32 traits -*- C++ -*-=// | 1 //===- subzero/src/IceTargetLoweringX8632Traits.h - x86-32 traits -*- C++ -*-=// |
2 // | 2 // |
3 // The Subzero Code Generator | 3 // The Subzero Code Generator |
4 // | 4 // |
5 // This file is distributed under the University of Illinois Open Source | 5 // This file is distributed under the University of Illinois Open Source |
6 // License. See LICENSE.TXT for details. | 6 // License. See LICENSE.TXT for details. |
7 // | 7 // |
8 //===----------------------------------------------------------------------===// | 8 //===----------------------------------------------------------------------===// |
9 /// | 9 /// |
10 /// \file | 10 /// \file |
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65 using XmmRegister = ::Ice::RegX8632::XmmRegister; | 65 using XmmRegister = ::Ice::RegX8632::XmmRegister; |
66 using X87STRegister = ::Ice::RegX8632::X87STRegister; | 66 using X87STRegister = ::Ice::RegX8632::X87STRegister; |
67 | 67 |
68 using Cond = ::Ice::CondX86; | 68 using Cond = ::Ice::CondX86; |
69 | 69 |
70 using RegisterSet = ::Ice::RegX8632; | 70 using RegisterSet = ::Ice::RegX8632; |
71 static const SizeT StackPtr = RegX8632::Reg_esp; | 71 static const SizeT StackPtr = RegX8632::Reg_esp; |
72 static const SizeT FramePtr = RegX8632::Reg_ebp; | 72 static const SizeT FramePtr = RegX8632::Reg_ebp; |
73 static const GPRRegister Encoded_Reg_Accumulator = RegX8632::Encoded_Reg_eax; | 73 static const GPRRegister Encoded_Reg_Accumulator = RegX8632::Encoded_Reg_eax; |
74 static const GPRRegister Encoded_Reg_Counter = RegX8632::Encoded_Reg_ecx; | 74 static const GPRRegister Encoded_Reg_Counter = RegX8632::Encoded_Reg_ecx; |
75 static const FixupKind PcRelFixup = llvm::ELF::R_386_PC32; | 75 static constexpr FixupKind FK_PcRel = llvm::ELF::R_386_PC32; |
76 static const FixupKind RelFixup = llvm::ELF::R_386_32; | 76 static constexpr FixupKind FK_Abs = llvm::ELF::R_386_32; |
| 77 static constexpr FixupKind FK_Gotoff = llvm::ELF::R_386_GOTOFF; |
| 78 static constexpr FixupKind FK_GotPC = llvm::ELF::R_386_GOTPC; |
77 | 79 |
78 class Operand { | 80 class Operand { |
79 public: | 81 public: |
80 Operand(const Operand &other) | 82 Operand(const Operand &other) |
81 : fixup_(other.fixup_), length_(other.length_) { | 83 : fixup_(other.fixup_), length_(other.length_) { |
82 memmove(&encoding_[0], &other.encoding_[0], other.length_); | 84 memmove(&encoding_[0], &other.encoding_[0], other.length_); |
83 } | 85 } |
84 | 86 |
85 Operand &operator=(const Operand &other) { | 87 Operand &operator=(const Operand &other) { |
86 length_ = other.length_; | 88 length_ = other.length_; |
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789 enum SegmentRegisters { | 791 enum SegmentRegisters { |
790 DefaultSegment = -1, | 792 DefaultSegment = -1, |
791 #define X(val, name, prefix) val, | 793 #define X(val, name, prefix) val, |
792 SEG_REGX8632_TABLE | 794 SEG_REGX8632_TABLE |
793 #undef X | 795 #undef X |
794 SegReg_NUM | 796 SegReg_NUM |
795 }; | 797 }; |
796 static X86OperandMem *create(Cfg *Func, Type Ty, Variable *Base, | 798 static X86OperandMem *create(Cfg *Func, Type Ty, Variable *Base, |
797 Constant *Offset, Variable *Index = nullptr, | 799 Constant *Offset, Variable *Index = nullptr, |
798 uint16_t Shift = 0, | 800 uint16_t Shift = 0, |
799 SegmentRegisters SegmentReg = DefaultSegment) { | 801 SegmentRegisters SegmentReg = DefaultSegment, |
800 return new (Func->allocate<X86OperandMem>()) | 802 bool IsPIC = false) { |
801 X86OperandMem(Func, Ty, Base, Offset, Index, Shift, SegmentReg); | 803 return new (Func->allocate<X86OperandMem>()) X86OperandMem( |
| 804 Func, Ty, Base, Offset, Index, Shift, SegmentReg, IsPIC); |
802 } | 805 } |
803 Variable *getBase() const { return Base; } | 806 Variable *getBase() const { return Base; } |
804 Constant *getOffset() const { return Offset; } | 807 Constant *getOffset() const { return Offset; } |
805 Variable *getIndex() const { return Index; } | 808 Variable *getIndex() const { return Index; } |
806 uint16_t getShift() const { return Shift; } | 809 uint16_t getShift() const { return Shift; } |
807 SegmentRegisters getSegmentRegister() const { return SegmentReg; } | 810 SegmentRegisters getSegmentRegister() const { return SegmentReg; } |
808 void emitSegmentOverride(Assembler *Asm) const; | 811 void emitSegmentOverride(Assembler *Asm) const; |
| 812 void setIsPIC() { IsPIC = true; } |
| 813 bool getIsPIC() const { return IsPIC; } |
809 Address toAsmAddress(Assembler *Asm, | 814 Address toAsmAddress(Assembler *Asm, |
810 const Ice::TargetLowering *Target) const; | 815 const Ice::TargetLowering *Target) const; |
811 | 816 |
812 void emit(const Cfg *Func) const override; | 817 void emit(const Cfg *Func) const override; |
813 using X86Operand::dump; | 818 using X86Operand::dump; |
814 void dump(const Cfg *Func, Ostream &Str) const override; | 819 void dump(const Cfg *Func, Ostream &Str) const override; |
815 | 820 |
816 static bool classof(const Operand *Operand) { | 821 static bool classof(const Operand *Operand) { |
817 return Operand->getKind() == static_cast<OperandKind>(kMem); | 822 return Operand->getKind() == static_cast<OperandKind>(kMem); |
818 } | 823 } |
819 | 824 |
820 void setRandomized(bool R) { Randomized = R; } | 825 void setRandomized(bool R) { Randomized = R; } |
821 | 826 |
822 bool getRandomized() const { return Randomized; } | 827 bool getRandomized() const { return Randomized; } |
823 | 828 |
824 private: | 829 private: |
825 X86OperandMem(Cfg *Func, Type Ty, Variable *Base, Constant *Offset, | 830 X86OperandMem(Cfg *Func, Type Ty, Variable *Base, Constant *Offset, |
826 Variable *Index, uint16_t Shift, SegmentRegisters SegmentReg); | 831 Variable *Index, uint16_t Shift, SegmentRegisters SegmentReg, |
| 832 bool IsPIC); |
827 | 833 |
828 Variable *Base; | 834 Variable *Base; |
829 Constant *Offset; | 835 Constant *Offset; |
830 Variable *Index; | 836 Variable *Index; |
831 uint16_t Shift; | 837 uint16_t Shift; |
832 SegmentRegisters SegmentReg : 16; | 838 SegmentRegisters SegmentReg : 16; |
| 839 bool IsPIC; |
833 /// A flag to show if this memory operand is a randomized one. Randomized | 840 /// A flag to show if this memory operand is a randomized one. Randomized |
834 /// memory operands are generated in | 841 /// memory operands are generated in |
835 /// TargetX86Base::randomizeOrPoolImmediate() | 842 /// TargetX86Base::randomizeOrPoolImmediate() |
836 bool Randomized; | 843 bool Randomized = false; |
837 }; | 844 }; |
838 | 845 |
839 /// VariableSplit is a way to treat an f64 memory location as a pair of i32 | 846 /// VariableSplit is a way to treat an f64 memory location as a pair of i32 |
840 /// locations (Low and High). This is needed for some cases of the Bitcast | 847 /// locations (Low and High). This is needed for some cases of the Bitcast |
841 /// instruction. Since it's not possible for integer registers to access the | 848 /// instruction. Since it's not possible for integer registers to access the |
842 /// XMM registers and vice versa, the lowering forces the f64 to be spilled to | 849 /// XMM registers and vice versa, the lowering forces the f64 to be spilled to |
843 /// the stack and then accesses through the VariableSplit. | 850 /// the stack and then accesses through the VariableSplit. |
844 // TODO(jpp): remove references to VariableSplit from IceInstX86Base as 64bit | 851 // TODO(jpp): remove references to VariableSplit from IceInstX86Base as 64bit |
845 // targets can natively handle these. | 852 // targets can natively handle these. |
846 class VariableSplit : public X86Operand { | 853 class VariableSplit : public X86Operand { |
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933 | 940 |
934 static uint8_t InstSegmentPrefixes[]; | 941 static uint8_t InstSegmentPrefixes[]; |
935 }; | 942 }; |
936 | 943 |
937 using Traits = ::Ice::X8632::TargetX8632Traits; | 944 using Traits = ::Ice::X8632::TargetX8632Traits; |
938 } // end of namespace X8632 | 945 } // end of namespace X8632 |
939 | 946 |
940 } // end of namespace Ice | 947 } // end of namespace Ice |
941 | 948 |
942 #endif // SUBZERO_SRC_ICETARGETLOWERINGX8632TRAITS_H | 949 #endif // SUBZERO_SRC_ICETARGETLOWERINGX8632TRAITS_H |
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