Subzero: Add Non-SFI support for x86-32.

src/IceTargetLoweringARM32.cpp

 //===- subzero/src/IceTargetLoweringARM32.cpp - ARM32 lowering ------------===//
 //
 //                        The Subzero Code Generator
 //
 // This file is distributed under the University of Illinois Open Source
 // License. See LICENSE.TXT for details.
 //
 //===----------------------------------------------------------------------===//
 ///
 /// \file
@@ skipping 32 matching lines @@
 std::unique_ptr<::Ice::TargetDataLowering>
 createTargetDataLowering(::Ice::GlobalContext *Ctx) {
   return ::Ice::ARM32::TargetDataARM32::create(Ctx);
 }
 
 std::unique_ptr<::Ice::TargetHeaderLowering>
 createTargetHeaderLowering(::Ice::GlobalContext *Ctx) {
   return ::Ice::ARM32::TargetHeaderARM32::create(Ctx);
 }
 
-void staticInit() { ::Ice::ARM32::TargetARM32::staticInit(); }
+void staticInit(const ::Ice::ClFlags &Flags) {
+  ::Ice::ARM32::TargetARM32::staticInit(Flags);
+}
 } // end of namespace ARM32
 
 namespace Ice {
 namespace ARM32 {
 
 // Defines the RegARM32::Table table with register information.
 constexpr RegARM32::TableType RegARM32::Table[];
 
 namespace {
 
@@ skipping 162 matching lines @@
     REGARM32_VEC128_TABLE
 #undef X
     ;
 std::array<uint32_t, NumVec128Args> Vec128ArgInitializer;
 } // end of anonymous namespace
 
 TargetARM32::TargetARM32(Cfg *Func)
     : TargetLowering(Func), NeedSandboxing(Ctx->getFlags().getUseSandboxing()),
       CPUFeatures(Func->getContext()->getFlags()) {}
 
-void TargetARM32::staticInit() {
+void TargetARM32::staticInit(const ClFlags &Flags) {
+  (void)Flags;
   // Limit this size (or do all bitsets need to be the same width)???
   llvm::SmallBitVector IntegerRegisters(RegARM32::Reg_NUM);
   llvm::SmallBitVector I64PairRegisters(RegARM32::Reg_NUM);
   llvm::SmallBitVector Float32Registers(RegARM32::Reg_NUM);
   llvm::SmallBitVector Float64Registers(RegARM32::Reg_NUM);
   llvm::SmallBitVector VectorRegisters(RegARM32::Reg_NUM);
   llvm::SmallBitVector InvalidRegisters(RegARM32::Reg_NUM);
   ScratchRegs.resize(RegARM32::Reg_NUM);
   for (int i = 0; i < RegARM32::Reg_NUM; ++i) {
     const auto &Entry = RegARM32::Table[i];
@@ skipping 643 matching lines @@
   }
   assert(!Var->isRematerializable());
   int32_t Offset = Var->getStackOffset();
   int32_t BaseRegNum = Var->getBaseRegNum();
   if (BaseRegNum == Variable::NoRegister) {
     BaseRegNum = getFrameOrStackReg();
   }
   const Type VarTy = Var->getType();
   Str << "[" << getRegName(BaseRegNum, VarTy);
   if (Offset != 0) {
-    Str << ", " << getConstantPrefix() << Offset;
+    Str << ", #" << Offset;
   }
   Str << "]";
 }
 
 TargetARM32::CallingConv::CallingConv()
     : GPRegsUsed(RegARM32::Reg_NUM),
       GPRArgs(GPRArgInitializer.rbegin(), GPRArgInitializer.rend()),
       I64Args(I64ArgInitializer.rbegin(), I64ArgInitializer.rend()),
       VFPRegsUsed(RegARM32::Reg_NUM),
       FP32Args(FP32ArgInitializer.rbegin(), FP32ArgInitializer.rend()),
@@ skipping 4788 matching lines @@
   (void)Permutation;
   (void)ExcludeRegisters;
   (void)Salt;
   UnimplementedError(Func->getContext()->getFlags());
 }
 
 void TargetARM32::emit(const ConstantInteger32 *C) const {
   if (!BuildDefs::dump())
     return;
   Ostream &Str = Ctx->getStrEmit();
-  Str << getConstantPrefix() << C->getValue();
+  Str << "#" << C->getValue();
 }
 
 void TargetARM32::emit(const ConstantInteger64 *) const {
   llvm::report_fatal_error("Not expecting to emit 64-bit integers");
 }
 
 void TargetARM32::emit(const ConstantFloat *C) const {
   (void)C;
   UnimplementedError(Ctx->getFlags());
 }
 
 void TargetARM32::emit(const ConstantDouble *C) const {
   (void)C;
   UnimplementedError(Ctx->getFlags());
 }
 
 void TargetARM32::emit(const ConstantUndef *) const {
   llvm::report_fatal_error("undef value encountered by emitter.");
 }
 
+void TargetARM32::emit(const ConstantRelocatable *C) const {
+  if (!BuildDefs::dump())
+    return;
+  Ostream &Str = Ctx->getStrEmit();
+  Str << "#";
+  emitWithoutPrefix(C);
+}
+
 void TargetARM32::lowerInt1ForSelect(Variable *Dest, Operand *Boolean,
                                      Operand *TrueValue, Operand *FalseValue) {
   Operand *_1 = legalize(Ctx->getConstantInt1(1), Legal_Reg | Legal_Flex);
 
   assert(Boolean->getType() == IceType_i1);
 
   bool NeedsAnd1 = false;
   if (TrueValue->getType() == IceType_i1) {
     assert(FalseValue->getType() == IceType_i1);
 
@@ skipping 504 matching lines @@
   if (Target->NeedSandboxing) {
     Target->_bic(SP, SP, memOpBicMask(Target->Func));
   }
 }
 
 TargetDataARM32::TargetDataARM32(GlobalContext *Ctx)
     : TargetDataLowering(Ctx) {}
 
 void TargetDataARM32::lowerGlobals(const VariableDeclarationList &Vars,
                                    const IceString &SectionSuffix) {
+  const bool IsPIC = Ctx->getFlags().getUseNonsfi();
   switch (Ctx->getFlags().getOutFileType()) {
   case FT_Elf: {
     ELFObjectWriter *Writer = Ctx->getObjectWriter();
-    Writer->writeDataSection(Vars, llvm::ELF::R_ARM_ABS32, SectionSuffix);
+    Writer->writeDataSection(Vars, llvm::ELF::R_ARM_ABS32, SectionSuffix,
+                             IsPIC);
   } break;
   case FT_Asm:
   case FT_Iasm: {
     const IceString &TranslateOnly = Ctx->getFlags().getTranslateOnly();
     OstreamLocker _(Ctx);
     for (const VariableDeclaration *Var : Vars) {
       if (GlobalContext::matchSymbolName(Var->getName(), TranslateOnly)) {
         emitGlobal(*Var, SectionSuffix);
       }
     }
@@ skipping 167 matching lines @@
   // However, for compatibility with current NaCl LLVM, don't claim that.
   Str << ".eabi_attribute 14, 3   @ Tag_ABI_PCS_R9_use: Not used\n";
 }
 
 llvm::SmallBitVector TargetARM32::TypeToRegisterSet[IceType_NUM];
 llvm::SmallBitVector TargetARM32::RegisterAliases[RegARM32::Reg_NUM];
 llvm::SmallBitVector TargetARM32::ScratchRegs;
 
 } // end of namespace ARM32
 } // end of namespace Ice