Subzero: Add Non-SFI support for x86-32.

src/IceAssemblerARM32.cpp

 //===- subzero/src/IceAssemblerARM32.cpp - Assembler for ARM32 --*- C++ -*-===//
 //
 // Copyright (c) 2013, the Dart project authors.  Please see the AUTHORS file
 // for details. All rights reserved. Use of this source code is governed by a
 // BSD-style license that can be found in the LICENSE file.
 //
 // Modified by the Subzero authors.
 //
 //===----------------------------------------------------------------------===//
 //
@@ skipping 481 matching lines @@
 size_t MoveRelocatableFixup::emit(GlobalContext *Ctx,
                                   const Assembler &Asm) const {
   if (!BuildDefs::dump())
     return InstARM32::InstSize;
   Ostream &Str = Ctx->getStrEmit();
   IValueT Inst = Asm.load<IValueT>(position());
   Str << "\t"
          "mov" << (kind() == llvm::ELF::R_ARM_MOVW_ABS_NC ? "w" : "t") << "\t"
       << RegARM32::getRegName((Inst >> kRdShift) & 0xF)
       << ", #:" << (kind() == llvm::ELF::R_ARM_MOVW_ABS_NC ? "lower" : "upper")
-      << "16:" << symbol(Ctx) << "\t@ .word "
+      << "16:" << symbol(Ctx, &Asm) << "\t@ .word "
       << llvm::format_hex_no_prefix(Inst, 8) << "\n";
   return InstARM32::InstSize;
 }
 
 MoveRelocatableFixup *AssemblerARM32::createMoveFixup(bool IsMovW,
                                                       const Constant *Value) {
   MoveRelocatableFixup *F =
       new (allocate<MoveRelocatableFixup>()) MoveRelocatableFixup();
   F->set_kind(IsMovW ? llvm::ELF::R_ARM_MOVW_ABS_NC
                      : llvm::ELF::R_ARM_MOVT_ABS);
   F->set_value(Value);
   Buffer.installFixup(F);
   return F;
 }
 
 size_t BlRelocatableFixup::emit(GlobalContext *Ctx,
                                 const Assembler &Asm) const {
   if (!BuildDefs::dump())
     return InstARM32::InstSize;
   Ostream &Str = Ctx->getStrEmit();
   IValueT Inst = Asm.load<IValueT>(position());
   Str << "\t"
-         "bl\t" << symbol(Ctx) << "\t@ .word "
+         "bl\t" << symbol(Ctx, &Asm) << "\t@ .word "
       << llvm::format_hex_no_prefix(Inst, 8) << "\n";
   return InstARM32::InstSize;
 }
 
 void AssemblerARM32::padWithNop(intptr_t Padding) {
   constexpr intptr_t InstWidth = sizeof(IValueT);
   assert(Padding % InstWidth == 0 &&
          "Padding not multiple of instruction size");
   for (intptr_t i = 0; i < Padding; i += InstWidth)
     nop();
@@ skipping 1515 matching lines @@
   // cccc11010D101101dddd1010iiiiiiii where cccc=Cond, ddddD=BaseReg, and
   // iiiiiiii=NumConsecRegs.
   constexpr const char *VpushName = "vpush";
   constexpr IValueT VpushOpcode =
       B27 | B26 | B24 | B21 | B19 | B18 | B16 | B11 | B9;
   emitVStackOp(Cond, VpushOpcode, OpBaseReg, NumConsecRegs, VpushName);
 }
 
 } // end of namespace ARM32
 } // end of namespace Ice