Subzero: Add Non-SFI support for x86-32.

src/IceTargetLoweringX86BaseImpl.h

 //===- subzero/src/IceTargetLoweringX86BaseImpl.h - x86 lowering -*- C++ -*-==//
 //
 //                        The Subzero Code Generator
 //
 // This file is distributed under the University of Illinois Open Source
 // License. See LICENSE.TXT for details.
 //
 //===----------------------------------------------------------------------===//
 ///
 /// \file
@@ skipping 306 matching lines @@
       "Traits::InstructionSet range different from TargetInstructionSet");
   if (Func->getContext()->getFlags().getTargetInstructionSet() !=
       TargetInstructionSet::BaseInstructionSet) {
     InstructionSet = static_cast<typename Traits::InstructionSet>(
         (Func->getContext()->getFlags().getTargetInstructionSet() -
          TargetInstructionSet::X86InstructionSet_Begin) +
         Traits::InstructionSet::Begin);
   }
 }
 
-template <class Machine> void TargetX86Base<Machine>::staticInit() {
+template <class Machine>
+void TargetX86Base<Machine>::staticInit(const ClFlags &Flags) {
   Traits::initRegisterSet(&TypeToRegisterSet, &RegisterAliases, &ScratchRegs);
+  PcRelFixup = Traits::FK_PcRel;
+  AbsFixup = Flags.getUseNonsfi() ? Traits::FK_Gotoff : Traits::FK_Abs;
 }
 
 template <class Machine> void TargetX86Base<Machine>::translateO2() {
   TimerMarker T(TimerStack::TT_O2, Func);
 
+  if (!Traits::Is64Bit && Func->getContext()->getFlags().getUseNonsfi()) {
+    GotVar = Func->makeVariable(IceType_i32);
+  }
   genTargetHelperCalls();
   Func->dump("After target helper call insertion");
 
   // Merge Alloca instructions, and lay out the stack.
   static constexpr bool SortAndCombineAllocas = true;
   Func->processAllocas(SortAndCombineAllocas);
   Func->dump("After Alloca processing");
 
   if (!Ctx->getFlags().getPhiEdgeSplit()) {
     // Lower Phi instructions.
@@ skipping 48 matching lines @@
   Func->dump("After x86 address mode opt");
 
   // Disable constant blinding or pooling for load optimization.
   {
     BoolFlagSaver B(RandomizationPoolingPaused, true);
     doLoadOpt();
   }
   Func->genCode();
   if (Func->hasError())
     return;
+  initGotVarIfNeeded();
   Func->dump("After x86 codegen");
 
   // Register allocation. This requires instruction renumbering and full
   // liveness analysis. Loops must be identified before liveness so variable
   // use weights are correct.
   Func->renumberInstructions();
   if (Func->hasError())
     return;
   Func->liveness(Liveness_Intervals);
   if (Func->hasError())
@@ skipping 38 matching lines @@
   Func->doNopInsertion();
 
   // Mark nodes that require sandbox alignment
   if (Ctx->getFlags().getUseSandboxing())
     Func->markNodesForSandboxing();
 }
 
 template <class Machine> void TargetX86Base<Machine>::translateOm1() {
   TimerMarker T(TimerStack::TT_Om1, Func);
 
+  if (!Traits::Is64Bit && Func->getContext()->getFlags().getUseNonsfi()) {
+    GotVar = Func->makeVariable(IceType_i32);
+  }
   genTargetHelperCalls();
 
   // Do not merge Alloca instructions, and lay out the stack.
   static constexpr bool SortAndCombineAllocas = false;
   Func->processAllocas(SortAndCombineAllocas);
   Func->dump("After Alloca processing");
 
   Func->placePhiLoads();
   if (Func->hasError())
     return;
   Func->placePhiStores();
   if (Func->hasError())
     return;
   Func->deletePhis();
   if (Func->hasError())
     return;
   Func->dump("After Phi lowering");
 
   Func->doArgLowering();
   Func->genCode();
   if (Func->hasError())
     return;
+  initGotVarIfNeeded();
   Func->dump("After initial x8632 codegen");
 
   regAlloc(RAK_InfOnly);
   if (Func->hasError())
     return;
   Func->dump("After regalloc of infinite-weight variables");
 
   Func->genFrame();
   if (Func->hasError())
     return;
@@ skipping 302 matching lines @@
 template <class Machine>
 void TargetX86Base<Machine>::emitVariable(const Variable *Var) const {
   if (!BuildDefs::dump())
     return;
   Ostream &Str = Ctx->getStrEmit();
   if (Var->hasReg()) {
     Str << "%" << getRegName(Var->getRegNum(), Var->getType());
     return;
   }
   if (Var->mustHaveReg()) {
-    llvm_unreachable("Infinite-weight Variable has no register assigned");
+    llvm::report_fatal_error(
+        "Infinite-weight Variable has no register assigned");
   }
   const int32_t Offset = Var->getStackOffset();
   int32_t BaseRegNum = Var->getBaseRegNum();
   if (BaseRegNum == Variable::NoRegister)
     BaseRegNum = getFrameOrStackReg();
   // Print in the form "Offset(%reg)", taking care that:
   //   - Offset is never printed when it is 0
 
   const bool DecorateAsm = Func->getContext()->getFlags().getDecorateAsm();
   // Only print Offset when it is nonzero, regardless of DecorateAsm.
   if (Offset) {
     if (DecorateAsm) {
       Str << Var->getSymbolicStackOffset(Func);
     } else {
       Str << Offset;
     }
   }
   const Type FrameSPTy = Traits::WordType;
   Str << "(%" << getRegName(BaseRegNum, FrameSPTy) << ")";
 }
 
 template <class Machine>
 typename TargetX86Base<Machine>::Traits::Address
 TargetX86Base<Machine>::stackVarToAsmOperand(const Variable *Var) const {
   if (Var->hasReg())
-    llvm_unreachable("Stack Variable has a register assigned");
+    llvm::report_fatal_error("Stack Variable has a register assigned");
   if (Var->mustHaveReg()) {
-    llvm_unreachable("Infinite-weight Variable has no register assigned");
+    llvm::report_fatal_error(
+        "Infinite-weight Variable has no register assigned");
   }
   int32_t Offset = Var->getStackOffset();
   int32_t BaseRegNum = Var->getBaseRegNum();
   if (Var->getBaseRegNum() == Variable::NoRegister)
     BaseRegNum = getFrameOrStackReg();
   return typename Traits::Address(Traits::getEncodedGPR(BaseRegNum), Offset,
                                   AssemblerFixup::NoFixup);
 }
 
 /// Helper function for addProlog().
@@ skipping 60 matching lines @@
     return Var64On32->getLo();
   if (auto *Const = llvm::dyn_cast<ConstantInteger64>(Operand)) {
     auto *ConstInt = llvm::dyn_cast<ConstantInteger32>(
         Ctx->getConstantInt32(static_cast<int32_t>(Const->getValue())));
     // Check if we need to blind/pool the constant.
     return legalize(ConstInt);
   }
   if (auto *Mem = llvm::dyn_cast<typename Traits::X86OperandMem>(Operand)) {
     auto *MemOperand = Traits::X86OperandMem::create(
         Func, IceType_i32, Mem->getBase(), Mem->getOffset(), Mem->getIndex(),
-        Mem->getShift(), Mem->getSegmentRegister());
+        Mem->getShift(), Mem->getSegmentRegister(), Mem->getIsPIC());
     // Test if we should randomize or pool the offset, if so randomize it or
     // pool it then create mem operand with the blinded/pooled constant.
     // Otherwise, return the mem operand as ordinary mem operand.
     return legalize(MemOperand);
   }
   llvm_unreachable("Unsupported operand type");
   return nullptr;
 }
 
 template <class Machine>
@@ skipping 19 matching lines @@
     } else if (auto *IntOffset = llvm::dyn_cast<ConstantInteger32>(Offset)) {
       Offset = Ctx->getConstantInt32(4 + IntOffset->getValue());
     } else if (auto *SymOffset = llvm::dyn_cast<ConstantRelocatable>(Offset)) {
       assert(!Utils::WouldOverflowAdd(SymOffset->getOffset(), 4));
       Offset =
           Ctx->getConstantSym(4 + SymOffset->getOffset(), SymOffset->getName(),
                               SymOffset->getSuppressMangling());
     }
     auto *MemOperand = Traits::X86OperandMem::create(
         Func, IceType_i32, Mem->getBase(), Offset, Mem->getIndex(),
-        Mem->getShift(), Mem->getSegmentRegister());
+        Mem->getShift(), Mem->getSegmentRegister(), Mem->getIsPIC());
     // Test if the Offset is an eligible i32 constants for randomization and
     // pooling. Blind/pool it if it is. Otherwise return as oridinary mem
     // operand.
     return legalize(MemOperand);
   }
   llvm_unreachable("Unsupported operand type");
   return nullptr;
 }
 
 template <class Machine>
 llvm::SmallBitVector
 TargetX86Base<Machine>::getRegisterSet(RegSetMask Include,
                                        RegSetMask Exclude) const {
   return Traits::getRegisterSet(Include, Exclude);
 }
 
+template <class Machine> void TargetX86Base<Machine>::initGotVarIfNeeded() {
+  if (!Func->getContext()->getFlags().getUseNonsfi())
+    return;
+  if (Traits::Is64Bit) {
+    // Probably no implementation is needed, but error to be safe for now.
+    llvm::report_fatal_error(
+        "Need to implement initGotVarIfNeeded() for 64-bit.");
+  }
+  // Insert the GotVar assignment as the very first lowered instruction.  Later,
+  // it will be moved into the right place - after the stack frame is set up but
+  // before in-args are copied into registers.
+  Context.init(Func->getEntryNode());
+  Context.setInsertPoint(Context.getCur());
+  Context.insert(InstX86GetIP<Machine>::create(Func, GotVar));
+}
+
 template <class Machine>
 void TargetX86Base<Machine>::lowerAlloca(const InstAlloca *Inst) {
   // Conservatively require the stack to be aligned. Some stack adjustment
   // operations implemented below assume that the stack is aligned before the
   // alloca. All the alloca code ensures that the stack alignment is preserved
   // after the alloca. The stack alignment restriction can be relaxed in some
   // cases.
   NeedsStackAlignment = true;
 
   // For default align=0, set it to the real value 1, to avoid any
@@ skipping 3011 matching lines @@
   }
   _test(SecondVar, SecondVar);
   _cmov(T_Dest2, T_Dest, Traits::Cond::Br_e);
   _mov(DestLo, T_Dest2);
   _mov(DestHi, Ctx->getConstantZero(IceType_i32));
 }
 
 template <class Machine>
 void TargetX86Base<Machine>::typedLoad(Type Ty, Variable *Dest, Variable *Base,
                                        Constant *Offset) {
+  // If Offset is a ConstantRelocatable in Non-SFI mode, we will need to
+  // legalize Mem properly.
+  if (Offset)
+    assert(!llvm::isa<ConstantRelocatable>(Offset));
+
   auto *Mem = Traits::X86OperandMem::create(Func, Ty, Base, Offset);
 
   if (isVectorType(Ty))
     _movp(Dest, Mem);
   else if (Ty == IceType_f64)
     _movq(Dest, Mem);
   else
     _mov(Dest, Mem);
 }
 
 template <class Machine>
 void TargetX86Base<Machine>::typedStore(Type Ty, Variable *Value,
                                         Variable *Base, Constant *Offset) {
+  // If Offset is a ConstantRelocatable in Non-SFI mode, we will need to
+  // legalize Mem properly.
+  if (Offset)
+    assert(!llvm::isa<ConstantRelocatable>(Offset));
+
   auto *Mem = Traits::X86OperandMem::create(Func, Ty, Base, Offset);
 
   if (isVectorType(Ty))
     _storep(Value, Mem);
   else if (Ty == IceType_f64)
     _storeq(Value, Mem);
   else
     _store(Value, Mem);
 }
 
@@ skipping 289 matching lines @@
     Str << "<null>";
   Str << ", Index=";
   if (Index)
     Index->dump(Func);
   else
     Str << "<null>";
   Str << ", Shift=" << Shift << ", Offset=" << Offset
       << ", Relocatable=" << Relocatable << "\n";
 }
 
-inline bool matchAssign(const VariablesMetadata *VMetadata, Variable *&Var,
-                        ConstantRelocatable *&Relocatable, int32_t &Offset,
-                        const Inst *&Reason) {
+inline bool matchAssign(const VariablesMetadata *VMetadata, Variable *GotVar,
+                        Variable *&Var, ConstantRelocatable *&Relocatable,
+                        int32_t &Offset, const Inst *&Reason) {
   // Var originates from Var=SrcVar ==> set Var:=SrcVar
   if (Var == nullptr)
     return false;
   if (const Inst *VarAssign = VMetadata->getSingleDefinition(Var)) {
     assert(!VMetadata->isMultiDef(Var));
     if (llvm::isa<InstAssign>(VarAssign)) {
       Operand *SrcOp = VarAssign->getSrc(0);
       assert(SrcOp);
       if (auto *SrcVar = llvm::dyn_cast<Variable>(SrcOp)) {
         if (!VMetadata->isMultiDef(SrcVar) &&
             // TODO: ensure SrcVar stays single-BB
             true) {
           Var = SrcVar;
           Reason = VarAssign;
           return true;
         }
       } else if (auto *Const = llvm::dyn_cast<ConstantInteger32>(SrcOp)) {
         int32_t MoreOffset = Const->getValue();
         if (Utils::WouldOverflowAdd(Offset, MoreOffset))
           return false;
         Var = nullptr;
         Offset += MoreOffset;
         Reason = VarAssign;
         return true;
       } else if (auto *AddReloc = llvm::dyn_cast<ConstantRelocatable>(SrcOp)) {
         if (Relocatable == nullptr) {
-          Var = nullptr;
+          Var = GotVar;
           Relocatable = AddReloc;
           Reason = VarAssign;
           return true;
         }
       }
     }
   }
   return false;
 }
 
@@ skipping 98 matching lines @@
             return true;
           }
         }
         }
       }
     }
   }
   return false;
 }
 
-inline bool matchOffsetBase(const VariablesMetadata *VMetadata, Variable *&Base,
+inline bool matchOffsetBase(const VariablesMetadata *VMetadata,
+                            Variable *GotVar, Variable *&Base,
+                            Variable *&BaseOther,
                             ConstantRelocatable *&Relocatable, int32_t &Offset,
                             const Inst *&Reason) {
   // Base is Base=Var+Const || Base is Base=Const+Var ==>
   //   set Base=Var, Offset+=Const
   // Base is Base=Var-Const ==>
   //   set Base=Var, Offset-=Const
   if (Base == nullptr) {
     return false;
   }
   const Inst *BaseInst = VMetadata->getSingleDefinition(Base);
@@ skipping 30 matching lines @@
     if ((Relocatable && (Reloc0 || Reloc1)) || (Reloc0 && Reloc1))
       return false;
     // Don't know how to subtract a relocatable.
     if (!IsAdd && Reloc1)
       return false;
     // Incorporate ConstantRelocatables.
     if (Reloc0)
       NewRelocatable = Reloc0;
     else if (Reloc1)
       NewRelocatable = Reloc1;
+    if ((Reloc0 || Reloc1) && BaseOther && GotVar)

[John, 2016/01/04 21:33:51]

add '!= nullptr'? or not. :)

[Jim Stichnoth, 2016/01/04 23:32:12]

hmm, maybe not, since this follows the style of the rest of the function...

+      return false;
     // Compute the updated constant offset.
     if (Const0) {
       int32_t MoreOffset = IsAdd ? Const0->getValue() : -Const0->getValue();
       if (Utils::WouldOverflowAdd(NewOffset, MoreOffset))
         return false;
       NewOffset += MoreOffset;
     }
     if (Const1) {
       int32_t MoreOffset = IsAdd ? Const1->getValue() : -Const1->getValue();
       if (Utils::WouldOverflowAdd(NewOffset, MoreOffset))
         return false;
       NewOffset += MoreOffset;
     }
     // Update the computed address parameters once we are sure optimization
     // is valid.
+    if ((Reloc0 || Reloc1) && GotVar) {
+      assert(BaseOther == nullptr);
+      BaseOther = GotVar;
+    }
     Base = NewBase;
     Offset = NewOffset;
     Relocatable = NewRelocatable;
     Reason = BaseInst;
     return true;
   }
   return false;
 }
 
 // Builds information for a canonical address expresion:
 //   <Relocatable + Offset>(Base, Index, Shift)
 // On entry:
 //   Relocatable == null,
 //   Offset == 0,
 //   Base is a Variable,
 //   Index == nullptr,
 //   Shift == 0
-inline bool computeAddressOpt(Cfg *Func, const Inst *Instr,
+inline bool computeAddressOpt(Cfg *Func, const Inst *Instr, Variable *GotVar,
                               ConstantRelocatable *&Relocatable,
                               int32_t &Offset, Variable *&Base,
                               Variable *&Index, uint16_t &Shift) {
   bool AddressWasOptimized = false;
   Func->resetCurrentNode();
   if (Func->isVerbose(IceV_AddrOpt)) {
     OstreamLocker L(Func->getContext());
     Ostream &Str = Func->getContext()->getStrDump();
     Str << "\nStarting computeAddressOpt for instruction:\n  ";
     Instr->dumpDecorated(Func);
@@ skipping 10 matching lines @@
   const bool MockBounds = Func->getContext()->getFlags().getMockBoundsCheck();
   const VariablesMetadata *VMetadata = Func->getVMetadata();
   const Inst *Reason = nullptr;
   do {
     if (Reason) {
       dumpAddressOpt(Func, Relocatable, Offset, Base, Index, Shift, Reason);
       AddressWasOptimized = true;
       Reason = nullptr;
     }
     // Update Base and Index to follow through assignments to definitions.
-    if (matchAssign(VMetadata, Base, Relocatable, Offset, Reason)) {
+    if (matchAssign(VMetadata, GotVar, Base, Relocatable, Offset, Reason)) {
       // Assignments of Base from a Relocatable or ConstantInt32 can result
       // in Base becoming nullptr.  To avoid code duplication in this loop we
       // prefer that Base be non-nullptr if possible.
       if ((Base == nullptr) && (Index != nullptr) && Shift == 0)
         std::swap(Base, Index);
       continue;
     }
-    if (matchAssign(VMetadata, Index, Relocatable, Offset, Reason))
+    if (matchAssign(VMetadata, GotVar, Index, Relocatable, Offset, Reason))
       continue;
 
     if (!MockBounds) {
       // Transition from:
       //   <Relocatable + Offset>(Base) to
       //   <Relocatable + Offset>(Base, Index)
       if (matchCombinedBaseIndex(VMetadata, Base, Index, Shift, Reason))
         continue;
       // Recognize multiply/shift and update Shift amount.
       // Index becomes Index=Var<<Const && Const+Shift<=3 ==>
       //   Index=Var, Shift+=Const
       // Index becomes Index=Const*Var && log2(Const)+Shift<=3 ==>
       //   Index=Var, Shift+=log2(Const)
       if (matchShiftedIndex(VMetadata, Index, Shift, Reason))
         continue;
       // If Shift is zero, the choice of Base and Index was purely arbitrary.
       // Recognize multiply/shift and set Shift amount.
       // Shift==0 && Base is Base=Var*Const && log2(Const)+Shift<=3 ==>
       //   swap(Index,Base)
       // Similar for Base=Const*Var and Base=Var<<Const
       if (Shift == 0 && matchShiftedIndex(VMetadata, Base, Shift, Reason)) {
         std::swap(Base, Index);
         continue;
       }
     }
     // Update Offset to reflect additions/subtractions with constants and
     // relocatables.
     // TODO: consider overflow issues with respect to Offset.
-    if (matchOffsetBase(VMetadata, Base, Relocatable, Offset, Reason))
+    if (matchOffsetBase(VMetadata, GotVar, Base, Index, Relocatable, Offset,
+                        Reason))
       continue;
-    if (Shift == 0 &&
-        matchOffsetBase(VMetadata, Index, Relocatable, Offset, Reason))
+    if (Shift == 0 && matchOffsetBase(VMetadata, GotVar, Index, Base,
+                                      Relocatable, Offset, Reason))
       continue;
     // TODO(sehr, stichnot): Handle updates of Index with Shift != 0.
     // Index is Index=Var+Const ==>
     //   set Index=Var, Offset+=(Const<<Shift)
     // Index is Index=Const+Var ==>
     //   set Index=Var, Offset+=(Const<<Shift)
     // Index is Index=Var-Const ==>
     //   set Index=Var, Offset-=(Const<<Shift)
     break;
   } while (Reason);
+  // Undo any addition of GotVar.  It will be added back when the mem operand is
+  // legalized.
+  if (Base == GotVar)
+    Base = nullptr;
+  if (Index == GotVar)
+    Index = nullptr;
   return AddressWasOptimized;
 }
 
 /// Add a mock bounds check on the memory address before using it as a load or
 /// store operand.  The basic idea is that given a memory operand [reg], we
 /// would first add bounds-check code something like:
 ///
 ///   cmp reg, <lb>
 ///   jl out_of_line_error
 ///   cmp reg, <ub>
@@ skipping 45 matching lines @@
   _br(Traits::Cond::Br_e, Label);
   _cmp(Opnd, Ctx->getConstantInt32(1));
   _br(Traits::Cond::Br_e, Label);
   Context.insert(Label);
 }
 
 template <class Machine>
 void TargetX86Base<Machine>::lowerLoad(const InstLoad *Load) {
   // A Load instruction can be treated the same as an Assign instruction, after
   // the source operand is transformed into an Traits::X86OperandMem operand.
-  // Note that the address mode optimization already creates an
+  // Note that the address mode optimization already creates a
   // Traits::X86OperandMem operand, so it doesn't need another level of
   // transformation.
   Variable *DestLoad = Load->getDest();
   Type Ty = DestLoad->getType();
   Operand *Src0 = formMemoryOperand(Load->getSourceAddress(), Ty);
   doMockBoundsCheck(Src0);
   auto *Assign = InstAssign::create(Func, DestLoad, Src0);
   lowerAssign(Assign);
 }
 
 template <class Machine> void TargetX86Base<Machine>::doAddressOptLoad() {
   Inst *Inst = Context.getCur();
   Variable *Dest = Inst->getDest();
   Operand *Addr = Inst->getSrc(0);
   Variable *Index = nullptr;
   ConstantRelocatable *Relocatable = nullptr;
   uint16_t Shift = 0;
   int32_t Offset = 0;
   // Vanilla ICE load instructions should not use the segment registers, and
   // computeAddressOpt only works at the level of Variables and Constants, not
   // other Traits::X86OperandMem, so there should be no mention of segment
   // registers there either.
-  const typename Traits::X86OperandMem::SegmentRegisters SegmentReg =
-      Traits::X86OperandMem::DefaultSegment;
+  constexpr auto SegmentReg =
+      Traits::X86OperandMem::SegmentRegisters::DefaultSegment;
   auto *Base = llvm::dyn_cast<Variable>(Addr);
-  if (computeAddressOpt(Func, Inst, Relocatable, Offset, Base, Index, Shift)) {
+  if (computeAddressOpt(Func, Inst, GotVar, Relocatable, Offset, Base, Index,
+                        Shift)) {
     Inst->setDeleted();
     Constant *OffsetOp = nullptr;
     if (Relocatable == nullptr) {
       OffsetOp = Ctx->getConstantInt32(Offset);
     } else {
       OffsetOp = Ctx->getConstantSym(Relocatable->getOffset() + Offset,
                                      Relocatable->getName(),
                                      Relocatable->getSuppressMangling());
     }
+    // The new mem operand is created without IsPIC being set, because
+    // computeAddressOpt() doesn't include GotVar in its final result.
     Addr = Traits::X86OperandMem::create(Func, Dest->getType(), Base, OffsetOp,
                                          Index, Shift, SegmentReg);
     Context.insert<InstLoad>(Dest, Addr);
   }
 }
 
 template <class Machine>
 void TargetX86Base<Machine>::randomlyInsertNop(float Probability,
                                                RandomNumberGenerator &RNG) {
   RandomNumberGeneratorWrapper RNGW(RNG);
@@ skipping 274 matching lines @@
   Operand *Addr = Inst->getAddr();
   Variable *Index = nullptr;
   ConstantRelocatable *Relocatable = nullptr;
   uint16_t Shift = 0;
   int32_t Offset = 0;
   auto *Base = llvm::dyn_cast<Variable>(Addr);
   // Vanilla ICE store instructions should not use the segment registers, and
   // computeAddressOpt only works at the level of Variables and Constants, not
   // other Traits::X86OperandMem, so there should be no mention of segment
   // registers there either.
-  const typename Traits::X86OperandMem::SegmentRegisters SegmentReg =
-      Traits::X86OperandMem::DefaultSegment;
-  if (computeAddressOpt(Func, Inst, Relocatable, Offset, Base, Index, Shift)) {
+  constexpr auto SegmentReg = Traits::X86OperandMem::DefaultSegment;
+  if (computeAddressOpt(Func, Inst, GotVar, Relocatable, Offset, Base, Index,

[John, 2016/01/04 21:33:51]

These address mode formation helpers are now better off as member functions
(this->Func, and this->GotVar are parameters.)

[Jim Stichnoth, 2016/01/04 23:32:12]

That seems good, but maybe as a follow-on CL?  Given that it should happen to
not only computeAddressOpt() but also all the helpers it calls.

+                        Shift)) {
     Inst->setDeleted();
     Constant *OffsetOp = nullptr;
     if (Relocatable == nullptr) {
       OffsetOp = Ctx->getConstantInt32(Offset);
     } else {
       OffsetOp = Ctx->getConstantSym(Relocatable->getOffset() + Offset,
                                      Relocatable->getName(),
                                      Relocatable->getSuppressMangling());
     }
+    // The new mem operand is created without IsPIC being set, because
+    // computeAddressOpt() doesn't include GotVar in its final result.
     Addr = Traits::X86OperandMem::create(Func, Data->getType(), Base, OffsetOp,
                                          Index, Shift, SegmentReg);
     auto *NewStore = Context.insert<InstStore>(Data, Addr);
     if (Inst->getDest())
       NewStore->setRmwBeacon(Inst->getRmwBeacon());
   }
 }
 
 template <class Machine>
 Operand *TargetX86Base<Machine>::lowerCmpRange(Operand *Comparison,
@@ skipping 40 matching lines @@
     Variable *Index;
     if (RangeIndex->getType() != getPointerType()) {
       Index = makeReg(getPointerType());
       _movzx(Index, RangeIndex);
     } else {
       Index = legalizeToReg(RangeIndex);
     }
 
     constexpr RelocOffsetT RelocOffset = 0;
     constexpr bool SuppressMangling = true;
+    const bool IsPIC = Ctx->getFlags().getUseNonsfi();
     IceString MangledName = Ctx->mangleName(Func->getFunctionName());
-    Constant *Base = Ctx->getConstantSym(
+    Variable *Base = IsPIC ? legalizeToReg(GotVar) : nullptr;
+    Constant *Offset = Ctx->getConstantSym(
         RelocOffset, InstJumpTable::makeName(MangledName, JumpTable->getId()),
         SuppressMangling);
-    Constant *Offset = nullptr;
     uint16_t Shift = typeWidthInBytesLog2(getPointerType());
-    // TODO(ascull): remove need for legalize by allowing null base in memop
+    constexpr auto Segment = Traits::X86OperandMem::DefaultSegment;
     auto *TargetInMemory = Traits::X86OperandMem::create(
-        Func, getPointerType(), legalizeToReg(Base), Offset, Index, Shift);
+        Func, getPointerType(), Base, Offset, Index, Shift, Segment, IsPIC);
     Variable *Target = nullptr;
     _mov(Target, TargetInMemory);
     lowerIndirectJump(Target);
 
     if (DefaultTarget == nullptr)
       Context.insert(SkipJumpTable);
     return;
   }
   case CaseCluster::Range: {
     if (Case.isUnitRange()) {
@@ skipping 310 matching lines @@
   if (const auto *RMW =
           llvm::dyn_cast<typename Traits::Insts::FakeRMW>(Instr)) {
     lowerRMW(RMW);
   } else {
     TargetLowering::lowerOther(Instr);
   }
 }
 
 /// Turn an i64 Phi instruction into a pair of i32 Phi instructions, to preserve
 /// integrity of liveness analysis. Undef values are also turned into zeroes,
-/// since loOperand() and hiOperand() don't expect Undef input.
+/// since loOperand() and hiOperand() don't expect Undef input.  Also, in
+/// Non-SFI mode, add a FakeUse(GotVar) for every pooled constant operand.
 template <class Machine> void TargetX86Base<Machine>::prelowerPhis() {
+  if (Ctx->getFlags().getUseNonsfi()) {
+    assert(GotVar);
+    CfgNode *Node = Context.getNode();
+    uint32_t GotVarUseCount = 0;
+    for (Inst &I : Node->getPhis()) {
+      auto *Phi = llvm::dyn_cast<InstPhi>(&I);
+      if (Phi->isDeleted())
+        continue;
+      for (SizeT I = 0; I < Phi->getSrcSize(); ++I) {
+        Operand *Src = Phi->getSrc(I);
+        // TODO(stichnot): This over-counts for +0.0, and under-counts for other
+        // kinds of pooling.
+        if (llvm::isa<ConstantRelocatable>(Src) ||
+            llvm::isa<ConstantFloat>(Src) || llvm::isa<ConstantDouble>(Src)) {
+          ++GotVarUseCount;
+        }
+      }
+    }
+    if (GotVarUseCount) {
+      Node->getInsts().push_front(InstFakeUse::create(Func, GotVar));
+    }
+  }
   if (Traits::Is64Bit) {
     // On x86-64 we don't need to prelower phis -- the architecture can handle
     // 64-bit integer natively.
     return;
   }
 
   // Pause constant blinding or pooling, blinding or pooling will be done later
   // during phi lowering assignments
   BoolFlagSaver B(RandomizationPoolingPaused, true);
   PhiLowering::prelowerPhis32Bit<TargetX86Base<Machine>>(
@@ skipping 460 matching lines @@
     _movp(Reg, Src);
   } else {
     _mov(Reg, Src);
   }
   return Reg;
 }
 
 template <class Machine>
 Operand *TargetX86Base<Machine>::legalize(Operand *From, LegalMask Allowed,
                                           int32_t RegNum) {
-  Type Ty = From->getType();
+  const bool UseNonsfi = Func->getContext()->getFlags().getUseNonsfi();
+  const Type Ty = From->getType();
   // Assert that a physical register is allowed. To date, all calls to
   // legalize() allow a physical register. If a physical register needs to be
   // explicitly disallowed, then new code will need to be written to force a
   // spill.
   assert(Allowed & Legal_Reg);
   // If we're asking for a specific physical register, make sure we're not
   // allowing any other operand kinds. (This could be future work, e.g. allow
   // the shl shift amount to be either an immediate or in ecx.)
   assert(RegNum == Variable::NoRegister || Allowed == Legal_Reg);
 
@@ skipping 13 matching lines @@
         }
       }
     }
   }
 
   if (auto *Mem = llvm::dyn_cast<typename Traits::X86OperandMem>(From)) {
     // Before doing anything with a Mem operand, we need to ensure that the
     // Base and Index components are in physical registers.
     Variable *Base = Mem->getBase();
     Variable *Index = Mem->getIndex();
+    Constant *Offset = Mem->getOffset();
     Variable *RegBase = nullptr;
     Variable *RegIndex = nullptr;
     if (Base) {
       RegBase = llvm::cast<Variable>(
           legalize(Base, Legal_Reg | Legal_Rematerializable));
     }
     if (Index) {
       RegIndex = llvm::cast<Variable>(
           legalize(Index, Legal_Reg | Legal_Rematerializable));
     }
+    // For Non-SFI mode, if the Offset field is a ConstantRelocatable, we
+    // replace either Base or Index with a legalized GotVar.  At emission time,
+    // the ConstantRelocatable will be emitted with the @GOTOFF relocation.
+    bool NeedPIC = false;
+    if (UseNonsfi && !Mem->getIsPIC() && Offset &&
+        llvm::isa<ConstantRelocatable>(Offset)) {
+      assert(!(Allowed & Legal_AddrAbs));
+      NeedPIC = true;
+      if (RegBase == nullptr) {
+        RegBase = legalizeToReg(GotVar);
+      } else if (RegIndex == nullptr) {
+        RegIndex = legalizeToReg(GotVar);
+      } else {
+        llvm::report_fatal_error(
+            "Either Base or Index must be unused in Non-SFI mode");
+      }
+    }
     if (Base != RegBase || Index != RegIndex) {
-      Mem = Traits::X86OperandMem::create(Func, Ty, RegBase, Mem->getOffset(),
-                                          RegIndex, Mem->getShift(),
-                                          Mem->getSegmentRegister());
+      Mem = Traits::X86OperandMem::create(Func, Ty, RegBase, Offset, RegIndex,
+                                          Mem->getShift(),
+                                          Mem->getSegmentRegister(), NeedPIC);
     }
 
     // For all Memory Operands, we do randomization/pooling here
     From = randomizeOrPoolImmediate(Mem);
 
     if (!(Allowed & Legal_Mem)) {
       From = copyToReg(From, RegNum);
     }
     return From;
   }
+
   if (auto *Const = llvm::dyn_cast<Constant>(From)) {
     if (llvm::isa<ConstantUndef>(Const)) {
       From = legalizeUndef(Const, RegNum);
       if (isVectorType(Ty))
         return From;
       Const = llvm::cast<Constant>(From);
     }
     // There should be no constants of vector type (other than undef).
     assert(!isVectorType(Ty));
 
@@ skipping 10 matching lines @@
 
     // If the operand is an 32 bit constant integer, we should check whether we
     // need to randomize it or pool it.
     if (auto *C = llvm::dyn_cast<ConstantInteger32>(Const)) {
       Operand *NewConst = randomizeOrPoolImmediate(C, RegNum);
       if (NewConst != Const) {
         return NewConst;
       }
     }
 
+    // If the operand is a ConstantRelocatable, and Legal_AddrAbs is not
+    // specified, and UseNonsfi is indicated, we need to add GotVar.
+    if (auto *CR = llvm::dyn_cast<ConstantRelocatable>(Const)) {
+      if (UseNonsfi && !(Allowed & Legal_AddrAbs)) {
+        assert(Ty == IceType_i32);
+        Variable *RegBase = legalizeToReg(GotVar);
+        Variable *NewVar = makeReg(Ty, RegNum);
+        auto *Mem = Traits::X86OperandMem::create(Func, Ty, RegBase, CR);
+        Mem->setIsPIC();
+        _lea(NewVar, Mem);
+        From = NewVar;
+      }
+    }
+
     // Convert a scalar floating point constant into an explicit memory
     // operand.
     if (isScalarFloatingType(Ty)) {
       if (auto *ConstFloat = llvm::dyn_cast<ConstantFloat>(Const)) {
         if (Utils::isPositiveZero(ConstFloat->getValue()))
           return makeZeroedRegister(Ty, RegNum);
       } else if (auto *ConstDouble = llvm::dyn_cast<ConstantDouble>(Const)) {
         if (Utils::isPositiveZero(ConstDouble->getValue()))
           return makeZeroedRegister(Ty, RegNum);
       }
-      Variable *Base = nullptr;
+      Variable *Base = UseNonsfi ? legalizeToReg(GotVar) : nullptr;
       std::string Buffer;
       llvm::raw_string_ostream StrBuf(Buffer);
       llvm::cast<Constant>(From)->emitPoolLabel(StrBuf, Ctx);
       llvm::cast<Constant>(From)->setShouldBePooled(true);
       Constant *Offset = Ctx->getConstantSym(0, StrBuf.str(), true);
-      From = Traits::X86OperandMem::create(Func, Ty, Base, Offset);
+      auto *Mem = Traits::X86OperandMem::create(Func, Ty, Base, Offset);
+      if (UseNonsfi)
+        Mem->setIsPIC();
+      From = Mem;
     }
     bool NeedsReg = false;
     if (!(Allowed & Legal_Imm) && !isScalarFloatingType(Ty))
       // Immediate specifically not allowed
       NeedsReg = true;
     if (!(Allowed & Legal_Mem) && isScalarFloatingType(Ty))
       // On x86, FP constants are lowered to mem operands.
       NeedsReg = true;
     if (NeedsReg) {
       From = copyToReg(From, RegNum);
     }
     return From;
   }
+
   if (auto *Var = llvm::dyn_cast<Variable>(From)) {
     // Check if the variable is guaranteed a physical register. This can happen
     // either when the variable is pre-colored or when it is assigned infinite
     // weight.
     bool MustHaveRegister = (Var->hasReg() || Var->mustHaveReg());
     bool MustRematerialize =
         (Var->isRematerializable() && !(Allowed & Legal_Rematerializable));
     // We need a new physical register for the operand if:
     // - Mem is not allowed and Var isn't guaranteed a physical register, or
     // - RegNum is required and Var->getRegNum() doesn't match, or
     // - Var is a rematerializable variable and rematerializable pass-through is
     //   not allowed (in which case we need an lea instruction).
     if (MustRematerialize) {
       assert(Ty == IceType_i32);
       Variable *NewVar = makeReg(Ty, RegNum);
       // Since Var is rematerializable, the offset will be added when the lea is
       // emitted.
       constexpr Constant *NoOffset = nullptr;
       auto *Mem = Traits::X86OperandMem::create(Func, Ty, Var, NoOffset);
       _lea(NewVar, Mem);
       From = NewVar;
     } else if ((!(Allowed & Legal_Mem) && !MustHaveRegister) ||
                (RegNum != Variable::NoRegister && RegNum != Var->getRegNum()) ||
                MustRematerialize) {
       From = copyToReg(From, RegNum);
     }
     return From;
   }
-  llvm_unreachable("Unhandled operand kind in legalize()");
+
+  llvm::report_fatal_error("Unhandled operand kind in legalize()");
   return From;
 }
 
 /// Provide a trivial wrapper to legalize() for this common usage.
 template <class Machine>
 Variable *TargetX86Base<Machine>::legalizeToReg(Operand *From, int32_t RegNum) {
   return llvm::cast<Variable>(legalize(From, Legal_Reg, RegNum));
 }
 
 /// Legalize undef values to concrete values.
@@ skipping 47 matching lines @@
   // transformation.
   if (!Mem) {
     auto *Base = llvm::dyn_cast<Variable>(Opnd);
     auto *Offset = llvm::dyn_cast<Constant>(Opnd);
     assert(Base || Offset);
     if (Offset) {
       // During memory operand building, we do not blind or pool the constant
       // offset, we will work on the whole memory operand later as one entity
       // later, this save one instruction. By turning blinding and pooling off,
       // we guarantee legalize(Offset) will return a Constant*.
-      {
+      if (!llvm::isa<ConstantRelocatable>(Offset)) {
         BoolFlagSaver B(RandomizationPoolingPaused, true);
 
         Offset = llvm::cast<Constant>(legalize(Offset));
       }
 
       assert(llvm::isa<ConstantInteger32>(Offset) ||
              llvm::isa<ConstantRelocatable>(Offset));
     }
+    // Not completely sure whether it's OK to leave IsPIC unset when creating
+    // the mem operand.  If DoLegalize is true, it will definitely be applied
+    // during the legalize() call, but perhaps not during the
+    // randomizeOrPoolImmediate() call.  In any case, the emit routines will
+    // assert that PIC legalization has been applied.
     Mem = Traits::X86OperandMem::create(Func, Ty, Base, Offset);
   }
   // Do legalization, which contains randomization/pooling or do
   // randomization/pooling.
   return llvm::cast<typename Traits::X86OperandMem>(
       DoLegalize ? legalize(Mem) : randomizeOrPoolImmediate(Mem));
 }
 
 template <class Machine>
 Variable *TargetX86Base<Machine>::makeReg(Type Type, int32_t RegNum) {
@@ skipping 47 matching lines @@
     const llvm::SmallBitVector &ExcludeRegisters, uint64_t Salt) const {
   Traits::makeRandomRegisterPermutation(Ctx, Func, Permutation,
                                         ExcludeRegisters, Salt);
 }
 
 template <class Machine>
 void TargetX86Base<Machine>::emit(const ConstantInteger32 *C) const {
   if (!BuildDefs::dump())
     return;
   Ostream &Str = Ctx->getStrEmit();
-  Str << getConstantPrefix() << C->getValue();
+  Str << "$" << C->getValue();
 }
 
 template <class Machine>
 void TargetX86Base<Machine>::emit(const ConstantInteger64 *C) const {
   if (!Traits::Is64Bit) {
     llvm::report_fatal_error("Not expecting to emit 64-bit integers");
   } else {
     if (!BuildDefs::dump())
       return;
     Ostream &Str = Ctx->getStrEmit();
-    Str << getConstantPrefix() << C->getValue();
+    Str << "$" << C->getValue();
   }
 }
 
 template <class Machine>
 void TargetX86Base<Machine>::emit(const ConstantFloat *C) const {
   if (!BuildDefs::dump())
     return;
   Ostream &Str = Ctx->getStrEmit();
   C->emitPoolLabel(Str, Ctx);
 }
 
 template <class Machine>
 void TargetX86Base<Machine>::emit(const ConstantDouble *C) const {
   if (!BuildDefs::dump())
     return;
   Ostream &Str = Ctx->getStrEmit();
   C->emitPoolLabel(Str, Ctx);
 }
 
 template <class Machine>
 void TargetX86Base<Machine>::emit(const ConstantUndef *) const {
   llvm::report_fatal_error("undef value encountered by emitter.");
 }
 
+template <class Machine>
+void TargetX86Base<Machine>::emit(const ConstantRelocatable *C) const {
+  if (!BuildDefs::dump())
+    return;
+  assert(!Ctx->getFlags().getUseNonsfi());
+  Ostream &Str = Ctx->getStrEmit();
+  Str << "$";
+  emitWithoutPrefix(C);
+}
+
 /// Randomize or pool an Immediate.
 template <class Machine>
 Operand *TargetX86Base<Machine>::randomizeOrPoolImmediate(Constant *Immediate,
                                                           int32_t RegNum) {
   assert(llvm::isa<ConstantInteger32>(Immediate) ||
          llvm::isa<ConstantRelocatable>(Immediate));
   if (Ctx->getFlags().getRandomizeAndPoolImmediatesOption() == RPI_None ||
       RandomizationPoolingPaused == true) {
     // Immediates randomization/pooling off or paused
     return Immediate;
@@ skipping 43 matching lines @@
       // assigned register as this assignment is that start of its use-def
       // chain. So we add RegNum argument here.
       Variable *Reg = makeReg(Immediate->getType(), RegNum);
       IceString Label;
       llvm::raw_string_ostream Label_stream(Label);
       Immediate->emitPoolLabel(Label_stream, Ctx);
       constexpr RelocOffsetT Offset = 0;
       constexpr bool SuppressMangling = true;
       Constant *Symbol =
           Ctx->getConstantSym(Offset, Label_stream.str(), SuppressMangling);
+      const bool UseNonsfi = Ctx->getFlags().getUseNonsfi();
+      Variable *Base = UseNonsfi ? legalizeToReg(GotVar) : nullptr;
       typename Traits::X86OperandMem *MemOperand =
-          Traits::X86OperandMem::create(Func, Immediate->getType(), nullptr,
+          Traits::X86OperandMem::create(Func, Immediate->getType(), Base,
                                         Symbol);
+      if (UseNonsfi)
+        MemOperand->setIsPIC();
       _mov(Reg, MemOperand);
       return Reg;
     }
     assert("Unsupported -randomize-pool-immediates option" && false);
   }
   // the constant Immediate is not eligible for blinding/pooling
   return Immediate;
 }
 
 template <class Machine>
@@ skipping 74 matching lines @@
           return MemOperand;
         Variable *RegTemp = makeReg(IceType_i32);
         IceString Label;
         llvm::raw_string_ostream Label_stream(Label);
         MemOperand->getOffset()->emitPoolLabel(Label_stream, Ctx);
         MemOperand->getOffset()->setShouldBePooled(true);
         constexpr RelocOffsetT SymOffset = 0;
         constexpr bool SuppressMangling = true;
         Constant *Symbol = Ctx->getConstantSym(SymOffset, Label_stream.str(),
                                                SuppressMangling);
+        const bool UseNonsfi = Ctx->getFlags().getUseNonsfi();
+        Variable *Base = UseNonsfi ? legalizeToReg(GotVar) : nullptr;
         typename Traits::X86OperandMem *SymbolOperand =
             Traits::X86OperandMem::create(
-                Func, MemOperand->getOffset()->getType(), nullptr, Symbol);
+                Func, MemOperand->getOffset()->getType(), Base, Symbol);
+        if (UseNonsfi)
+          SymbolOperand->setIsPIC();
         _mov(RegTemp, SymbolOperand);
         // If we have a base variable here, we should add the lea instruction
         // to add the value of the base variable to RegTemp. If there is no
         // base variable, we won't need this lea instruction.
         if (MemOperand->getBase()) {
           typename Traits::X86OperandMem *CalculateOperand =
               Traits::X86OperandMem::create(
                   Func, MemOperand->getType(), MemOperand->getBase(), nullptr,
                   RegTemp, 0, MemOperand->getSegmentRegister());
           _lea(RegTemp, CalculateOperand);
@@ skipping 10 matching lines @@
   }
   // the offset is not eligible for blinding or pooling, return the original
   // mem operand
   return MemOperand;
 }
 
 } // end of namespace X86Internal
 } // end of namespace Ice
 
 #endif // SUBZERO_SRC_ICETARGETLOWERINGX86BASEIMPL_H