Subzero: Add Non-SFI support for x86-32.

src/IceTargetLoweringX8664Traits.h

 //===- subzero/src/IceTargetLoweringX8664Traits.h - x86-64 traits -*- C++ -*-=//
 //
 //                        The Subzero Code Generator
 //
 // This file is distributed under the University of Illinois Open Source
 // License. See LICENSE.TXT for details.
 //
 //===----------------------------------------------------------------------===//
 ///
 /// \file
@@ skipping 53 matching lines @@
   using ByteRegister = ::Ice::RegX8664::ByteRegister;
   using XmmRegister = ::Ice::RegX8664::XmmRegister;
 
   using Cond = ::Ice::CondX8664;
 
   using RegisterSet = ::Ice::RegX8664;
   static const SizeT StackPtr = RegX8664::Reg_rsp;
   static const SizeT FramePtr = RegX8664::Reg_rbp;
   static const GPRRegister Encoded_Reg_Accumulator = RegX8664::Encoded_Reg_eax;
   static const GPRRegister Encoded_Reg_Counter = RegX8664::Encoded_Reg_ecx;
-  static const FixupKind PcRelFixup = llvm::ELF::R_X86_64_PC32;
-  static const FixupKind RelFixup = llvm::ELF::R_X86_64_32;
+  static constexpr FixupKind FK_PcRel = llvm::ELF::R_X86_64_PC32;
+  static constexpr FixupKind FK_Abs = llvm::ELF::R_X86_64_32;
+  static constexpr FixupKind FK_Gotoff = llvm::ELF::R_X86_64_GOTOFF64;
+  static constexpr FixupKind FK_GotPC = llvm::ELF::R_X86_64_GOTPC32;
 
   class Operand {
   public:
     enum RexBits {
       RexNone = 0x00,
       RexBase = 0x40,
       RexW = RexBase | (1 << 3),
       RexR = RexBase | (1 << 2),
       RexX = RexBase | (1 << 1),
       RexB = RexBase | (1 << 0),
@@ skipping 177 matching lines @@
       SetSIB(Scale, RegX8664::Encoded_Reg_esp, RegX8664::Encoded_Reg_ebp);
       // Use the Offset in the displacement for now. If we decide to process
       // fixups later, we'll need to patch up the emitted displacement.
       SetDisp32(Offset);
       if (Fixup)
         SetFixup(Fixup);
     }
 
     static Address ofConstPool(Assembler *Asm, const Constant *Imm) {
       // TODO(jpp): ???
-      AssemblerFixup *Fixup = Asm->createFixup(RelFixup, Imm);
+      AssemblerFixup *Fixup = Asm->createFixup(FK_Abs, Imm);
       const RelocOffsetT Offset = 4;
       return Address(Offset, Fixup);
     }
   };
 
   //----------------------------------------------------------------------------
   //     __      ______  __     __  ______  ______  __  __   __  ______
   //    /\ \    /\  __ \/\ \  _ \ \/\  ___\/\  == \/\ \/\ "-.\ \/\  ___\
   //    \ \ \___\ \ \/\ \ \ \/ ".\ \ \  __\\ \  __<\ \ \ \ \-.  \ \ \__ \
   //     \ \_____\ \_____\ \__/".~\_\ \_____\ \_\ \_\ \_\ \_\\"\_\ \_____\
@@ skipping 489 matching lines @@
   class X86OperandMem : public X86Operand {
     X86OperandMem() = delete;
     X86OperandMem(const X86OperandMem &) = delete;
     X86OperandMem &operator=(const X86OperandMem &) = delete;
 
   public:
     enum SegmentRegisters { DefaultSegment = -1, SegReg_NUM };
     static X86OperandMem *
     create(Cfg *Func, Type Ty, Variable *Base, Constant *Offset,
            Variable *Index = nullptr, uint16_t Shift = 0,
-           SegmentRegisters SegmentRegister = DefaultSegment) {
+           SegmentRegisters SegmentRegister = DefaultSegment,
+           bool IsPIC = false) {
       assert(SegmentRegister == DefaultSegment);
       (void)SegmentRegister;
       return new (Func->allocate<X86OperandMem>())
-          X86OperandMem(Func, Ty, Base, Offset, Index, Shift);
+          X86OperandMem(Func, Ty, Base, Offset, Index, Shift, IsPIC);
     }
     Variable *getBase() const { return Base; }
     Constant *getOffset() const { return Offset; }
     Variable *getIndex() const { return Index; }
     uint16_t getShift() const { return Shift; }
     SegmentRegisters getSegmentRegister() const { return DefaultSegment; }
     void emitSegmentOverride(Assembler *) const {}
+    void setIsPIC() { IsPIC = true; }
+    bool getIsPIC() const { return IsPIC; }
     Address toAsmAddress(Assembler *Asm,
                          const Ice::TargetLowering *Target) const;
 
     void emit(const Cfg *Func) const override;
     using X86Operand::dump;
     void dump(const Cfg *Func, Ostream &Str) const override;
 
     static bool classof(const Operand *Operand) {
       return Operand->getKind() == static_cast<OperandKind>(kMem);
     }
 
     void setRandomized(bool R) { Randomized = R; }
 
     bool getRandomized() const { return Randomized; }
 
   private:
     X86OperandMem(Cfg *Func, Type Ty, Variable *Base, Constant *Offset,
-                  Variable *Index, uint16_t Shift);
+                  Variable *Index, uint16_t Shift, bool IsPIC);
 
     Variable *Base;
     Constant *Offset;
     Variable *Index;
     uint16_t Shift;
+    bool IsPIC;
     /// A flag to show if this memory operand is a randomized one. Randomized
     /// memory operands are generated in
     /// TargetX86Base::randomizeOrPoolImmediate()
     bool Randomized = false;
   };
 
   /// VariableSplit is a way to treat an f64 memory location as a pair of i32
   /// locations (Low and High). This is needed for some cases of the Bitcast
   /// instruction. Since it's not possible for integer registers to access the
   /// XMM registers and vice versa, the lowering forces the f64 to be spilled to
@@ skipping 89 matching lines @@
 
 } // end of namespace X86Internal
 
 namespace X8664 {
 using Traits = ::Ice::X86Internal::MachineTraits<TargetX8664>;
 } // end of namespace X8664
 
 } // end of namespace Ice
 
 #endif // SUBZERO_SRC_ICETARGETLOWERINGX8664TRAITS_H