Subzero: Add Non-SFI support for x86-32.

src/IceTargetLoweringX8632Traits.h

 //===- subzero/src/IceTargetLoweringX8632Traits.h - x86-32 traits -*- C++ -*-=//
 //
 //                        The Subzero Code Generator
 //
 // This file is distributed under the University of Illinois Open Source
 // License. See LICENSE.TXT for details.
 //
 //===----------------------------------------------------------------------===//
 ///
 /// \file
@@ skipping 54 matching lines @@
   using XmmRegister = ::Ice::RegX8632::XmmRegister;
   using X87STRegister = ::Ice::RegX8632::X87STRegister;
 
   using Cond = ::Ice::CondX86;
 
   using RegisterSet = ::Ice::RegX8632;
   static const SizeT StackPtr = RegX8632::Reg_esp;
   static const SizeT FramePtr = RegX8632::Reg_ebp;
   static const GPRRegister Encoded_Reg_Accumulator = RegX8632::Encoded_Reg_eax;
   static const GPRRegister Encoded_Reg_Counter = RegX8632::Encoded_Reg_ecx;
-  static const FixupKind PcRelFixup = llvm::ELF::R_386_PC32;
-  static const FixupKind RelFixup = llvm::ELF::R_386_32;
+  static constexpr FixupKind FK_PcRel = llvm::ELF::R_386_PC32;
+  static constexpr FixupKind FK_Abs = llvm::ELF::R_386_32;
+  static constexpr FixupKind FK_Gotoff = llvm::ELF::R_386_GOTOFF;
+  static constexpr FixupKind FK_GotPC = llvm::ELF::R_386_GOTPC;
 
   class Operand {
   public:
     Operand(const Operand &other)
         : fixup_(other.fixup_), length_(other.length_) {
       memmove(&encoding_[0], &other.encoding_[0], other.length_);
     }
 
     Operand &operator=(const Operand &other) {
       length_ = other.length_;
@@ skipping 643 matching lines @@
     enum SegmentRegisters {
       DefaultSegment = -1,
 #define X(val, name, prefix) val,
       SEG_REGX8632_TABLE
 #undef X
           SegReg_NUM
     };
     static X86OperandMem *create(Cfg *Func, Type Ty, Variable *Base,
                                  Constant *Offset, Variable *Index = nullptr,
                                  uint16_t Shift = 0,
-                                 SegmentRegisters SegmentReg = DefaultSegment) {
-      return new (Func->allocate<X86OperandMem>())
-          X86OperandMem(Func, Ty, Base, Offset, Index, Shift, SegmentReg);
+                                 SegmentRegisters SegmentReg = DefaultSegment,
+                                 bool IsPIC = false) {
+      return new (Func->allocate<X86OperandMem>()) X86OperandMem(
+          Func, Ty, Base, Offset, Index, Shift, SegmentReg, IsPIC);
     }
     Variable *getBase() const { return Base; }
     Constant *getOffset() const { return Offset; }
     Variable *getIndex() const { return Index; }
     uint16_t getShift() const { return Shift; }
     SegmentRegisters getSegmentRegister() const { return SegmentReg; }
     void emitSegmentOverride(Assembler *Asm) const;
+    void setIsPIC() { IsPIC = true; }
+    bool getIsPIC() const { return IsPIC; }
     Address toAsmAddress(Assembler *Asm,
                          const Ice::TargetLowering *Target) const;
 
     void emit(const Cfg *Func) const override;
     using X86Operand::dump;
     void dump(const Cfg *Func, Ostream &Str) const override;
 
     static bool classof(const Operand *Operand) {
       return Operand->getKind() == static_cast<OperandKind>(kMem);
     }
 
     void setRandomized(bool R) { Randomized = R; }
 
     bool getRandomized() const { return Randomized; }
 
   private:
     X86OperandMem(Cfg *Func, Type Ty, Variable *Base, Constant *Offset,
-                  Variable *Index, uint16_t Shift, SegmentRegisters SegmentReg);
+                  Variable *Index, uint16_t Shift, SegmentRegisters SegmentReg,
+                  bool IsPIC);
 
     Variable *Base;
     Constant *Offset;
     Variable *Index;
     uint16_t Shift;
     SegmentRegisters SegmentReg : 16;
+    bool IsPIC;
     /// A flag to show if this memory operand is a randomized one. Randomized
     /// memory operands are generated in
     /// TargetX86Base::randomizeOrPoolImmediate()
-    bool Randomized;
+    bool Randomized = false;
   };
 
   /// VariableSplit is a way to treat an f64 memory location as a pair of i32
   /// locations (Low and High). This is needed for some cases of the Bitcast
   /// instruction. Since it's not possible for integer registers to access the
   /// XMM registers and vice versa, the lowering forces the f64 to be spilled to
   /// the stack and then accesses through the VariableSplit.
   // TODO(jpp): remove references to VariableSplit from IceInstX86Base as 64bit
   // targets can natively handle these.
   class VariableSplit : public X86Operand {
@@ skipping 89 matching lines @@
 
 } // end of namespace X86Internal
 
 namespace X8632 {
 using Traits = ::Ice::X86Internal::MachineTraits<TargetX8632>;
 } // end of namespace X8632
 
 } // end of namespace Ice
 
 #endif // SUBZERO_SRC_ICETARGETLOWERINGX8632TRAITS_H