Subzero: Add Non-SFI support for x86-32.

src/IceTargetLoweringX86Base.h

 //===- subzero/src/IceTargetLoweringX86Base.h - x86 lowering ----*- C++ -*-===//
 //
 //                        The Subzero Code Generator
 //
 // This file is distributed under the University of Illinois Open Source
 // License. See LICENSE.TXT for details.
 //
 //===----------------------------------------------------------------------===//
 ///
 /// \file
@@ skipping 41 matching lines @@
   TargetX86Base() = delete;
   TargetX86Base(const TargetX86Base &) = delete;
   TargetX86Base &operator=(const TargetX86Base &) = delete;
 
 public:
   using Traits = MachineTraits<Machine>;
   using BoolFolding = ::Ice::X86Internal::BoolFolding<Traits>;
 
   ~TargetX86Base() override = default;
 
-  static void staticInit();
+  static void staticInit(const ClFlags &Flags);
   static TargetX86Base *create(Cfg *Func) { return new TargetX86Base(Func); }
 
+  static FixupKind getPcRelFixup() { return PcRelFixup; }
+  static FixupKind getRelFixup() { return RelFixup; }
+
   void translateOm1() override;
   void translateO2() override;
   void doLoadOpt();
   bool doBranchOpt(Inst *I, const CfgNode *NextNode) override;
 
   SizeT getNumRegisters() const override {
     return Traits::RegisterSet::Reg_NUM;
   }
   Variable *getPhysicalRegister(SizeT RegNum, Type Ty = IceType_void) override;
   IceString getRegName(SizeT RegNum, Type Ty) const override;
@@ skipping 44 matching lines @@
   }
 
   bool shouldSplitToVariable64On32(Type Ty) const override {
     return Traits::Is64Bit ? false : Ty == IceType_i64;
   }
 
   SizeT getMinJumpTableSize() const override { return 4; }
 
   void emitVariable(const Variable *Var) const override;
 
-  const char *getConstantPrefix() const final { return "$"; }
-  void emit(const ConstantUndef *C) const final;
   void emit(const ConstantInteger32 *C) const final;
   void emit(const ConstantInteger64 *C) const final;
   void emit(const ConstantFloat *C) const final;
   void emit(const ConstantDouble *C) const final;
+  void emit(const ConstantUndef *C) const final;
+  void emit(const ConstantRelocatable *C) const final;
 
   void initNodeForLowering(CfgNode *Node) override;
 
   template <typename T = Traits>
   typename std::enable_if<!T::Is64Bit, Operand>::type *
   loOperand(Operand *Operand);
   template <typename T = Traits>
   typename std::enable_if<T::Is64Bit, Operand>::type *loOperand(Operand *) {
     llvm::report_fatal_error(
         "Hey, yo! This is x86-64. Watcha doin'? (loOperand)");
@@ skipping 113 matching lines @@
   /// that the Operand kind is one of those indicated by the LegalMask (a
   /// bitmask of allowed kinds). If the input Operand is known to already meet
   /// the constraints, it may be simply returned as the result, without creating
   /// any new instructions or operands.
   enum OperandLegalization {
     Legal_None = 0,
     Legal_Reg = 1 << 0, // physical register, not stack location
     Legal_Imm = 1 << 1,
     Legal_Mem = 1 << 2, // includes [eax+4*ecx] as well as [esp+12]
     Legal_Rematerializable = 1 << 3,
-    Legal_All = ~Legal_Rematerializable
+    Legal_AddrAbs = 1 << 4, // ConstantRelocatable doesn't have to add GotVar
+    Legal_Default = ~(Legal_Rematerializable | Legal_AddrAbs)
+    // TODO(stichnot): Figure out whether this default works for x86-64.
   };
   using LegalMask = uint32_t;
-  Operand *legalize(Operand *From, LegalMask Allowed = Legal_All,
+  Operand *legalize(Operand *From, LegalMask Allowed = Legal_Default,
                     int32_t RegNum = Variable::NoRegister);
   Variable *legalizeToReg(Operand *From, int32_t RegNum = Variable::NoRegister);
   /// Legalize the first source operand for use in the cmp instruction.
   Operand *legalizeSrc0ForCmp(Operand *Src0, Operand *Src1);
   /// Turn a pointer operand into a memory operand that can be used by a real
   /// load/store operation. Legalizes the operand as well. This is a nop if the
   /// operand is already a legal memory operand.
   typename Traits::X86OperandMem *formMemoryOperand(Operand *Ptr, Type Ty,
                                                     bool DoLegalize = true);
 
@@ skipping 442 matching lines @@
   size_t FixedAllocaSizeBytes = 0;
   size_t FixedAllocaAlignBytes = 0;
   bool PrologEmitsFixedAllocas = false;
   uint32_t MaxOutArgsSizeBytes = 0;
   static std::array<llvm::SmallBitVector, RCX86_NUM> TypeToRegisterSet;
   static std::array<llvm::SmallBitVector, Traits::RegisterSet::Reg_NUM>
       RegisterAliases;
   static llvm::SmallBitVector ScratchRegs;
   llvm::SmallBitVector RegsUsed;
   std::array<VarList, IceType_NUM> PhysicalRegisters;
+  // GotVar is a Variable that holds the GlobalOffsetTable address for Non-SFI
+  // mode.
+  Variable *GotVar = nullptr;
 
   /// Randomize a given immediate operand
   Operand *randomizeOrPoolImmediate(Constant *Immediate,
                                     int32_t RegNum = Variable::NoRegister);
   typename Traits::X86OperandMem *
   randomizeOrPoolImmediate(typename Traits::X86OperandMem *MemOperand,
                            int32_t RegNum = Variable::NoRegister);
   bool RandomizationPoolingPaused = false;
 
 private:
@@ skipping 46 matching lines @@
   void lowerSelectMove(Variable *Dest, typename Traits::Cond::BrCond Cond,
                        Operand *SrcT, Operand *SrcF);
   void lowerSelectIntMove(Variable *Dest, typename Traits::Cond::BrCond Cond,
                           Operand *SrcT, Operand *SrcF);
   /// Generic helper to move an arbitrary type from Src to Dest.
   void lowerMove(Variable *Dest, Operand *Src, bool IsRedefinition);
 
   /// Optimizations for idiom recognition.
   bool lowerOptimizeFcmpSelect(const InstFcmp *Fcmp, const InstSelect *Select);
 
+  /// Emit code that initializes the value of the GotVar near the start of the
+  /// function.
+  void initGotVar();
+
   /// Complains loudly if invoked because the cpu can handle 64-bit types
   /// natively.
   template <typename T = Traits>
   typename std::enable_if<T::Is64Bit, void>::type lowerIcmp64(const InstIcmp *,
                                                               const Inst *) {
     llvm::report_fatal_error(
         "Hey, yo! This is x86-64. Watcha doin'? (lowerIcmp64)");
   }
   /// x86lowerIcmp64 handles 64-bit icmp lowering.
   template <typename T = Traits>
   typename std::enable_if<!T::Is64Bit, void>::type
   lowerIcmp64(const InstIcmp *Icmp, const Inst *Consumer);
 
   BoolFolding FoldingInfo;
+
+  static FixupKind PcRelFixup;

[John, 2015/12/22 15:44:38]

This **really** belong in the Traits classes...

[Jim Stichnoth, 2015/12/28 07:54:07]

The issue here is that the fixup kind used for RelFixup depends on whether we
are generating PIC.  I thought Traits were more about holding const values,
constexpr values, and methods, so I put RelFixup as a static class member.  And
I did the same for PcRelFixup for consistency, even though it could just as well
be a constexpr trait.

I'm not very traits-savvy, so I would appreciate specific guidance here.

+  static FixupKind RelFixup;
 };
 } // end of namespace X86Internal
 } // end of namespace Ice
 
 #include "IceTargetLoweringX86BaseImpl.h"
 
 #endif // SUBZERO_SRC_ICETARGETLOWERINGX86BASE_H