Subzero: Add Non-SFI support for x86-32.

src/IceTargetLoweringX8632.cpp

 //===- subzero/src/IceTargetLoweringX8632.cpp - x86-32 lowering -----------===//
 //
 //                        The Subzero Code Generator
 //
 // This file is distributed under the University of Illinois Open Source
 // License. See LICENSE.TXT for details.
 //
 //===----------------------------------------------------------------------===//
 ///
 /// \file
@@ skipping 81 matching lines @@
 
 template <>
 std::array<llvm::SmallBitVector,
            TargetX86Base<TargetX8632>::Traits::RegisterSet::Reg_NUM>
     TargetX86Base<TargetX8632>::RegisterAliases = {{}};
 
 template <>
 llvm::SmallBitVector
     TargetX86Base<TargetX8632>::ScratchRegs = llvm::SmallBitVector();
 
+template <>
+FixupKind TargetX86Base<TargetX8632>::PcRelFixup =

[John, 2015/12/22 15:44:38]

I know this will be painful to change, but pic(k) one naming scheme or the
other, and use it everywhere.

[Jim Stichnoth, 2015/12/28 07:54:07]

New naming scheme described in a previous comment.

Also, I changed "RelFixup" to be the more accurate (I think) "AbsFixup".

+    TargetX86Base<TargetX8632>::Traits::FixupKindPcRel;
+
+template <>
+FixupKind TargetX86Base<TargetX8632>::RelFixup =
+    TargetX86Base<TargetX8632>::Traits::FixupKindAbs;
+
 } // end of namespace X86Internal
 
 //------------------------------------------------------------------------------
 //     __      ______  __     __  ______  ______  __  __   __  ______
 //    /\ \    /\  __ \/\ \  _ \ \/\  ___\/\  == \/\ \/\ "-.\ \/\  ___\
 //    \ \ \___\ \ \/\ \ \ \/ ".\ \ \  __\\ \  __<\ \ \ \ \-.  \ \ \__ \
 //     \ \_____\ \_____\ \__/".~\_\ \_____\ \_\ \_\ \_\ \_\\"\_\ \_____\
 //      \/_____/\/_____/\/_/   \/_/\/_____/\/_/ /_/\/_/\/_/ \/_/\/_____/
 //
 //------------------------------------------------------------------------------
@@ skipping 110 matching lines @@
     case IceType_v8i1:
     case IceType_v16i1:
     case IceType_v16i8:
     case IceType_v8i16:
     case IceType_v4i32:
     case IceType_v4f32:
       ReturnReg = makeReg(Dest->getType(), Traits::RegisterSet::Reg_xmm0);
       break;
     }
   }
-  Operand *CallTarget = legalize(Instr->getCallTarget());
+  Operand *CallTarget =
+      legalize(Instr->getCallTarget(), Legal_Reg | Legal_Imm | Legal_AddrAbs);
   const bool NeedSandboxing = Ctx->getFlags().getUseSandboxing();
   if (NeedSandboxing) {
     if (llvm::isa<Constant>(CallTarget)) {
       _bundle_lock(InstBundleLock::Opt_AlignToEnd);
     } else {
       Variable *CallTargetVar = nullptr;
       _mov(CallTargetVar, CallTarget);
       _bundle_lock(InstBundleLock::Opt_AlignToEnd);
       const SizeT BundleSize =
           1 << Func->getAssembler<>()->getBundleAlignLog2Bytes();
@@ skipping 153 matching lines @@
   // registers (as a side effect, this gives variables a second chance at
   // physical register assignment).
   //
   // A middle ground approach is to leverage sparsity and allocate one block of
   // space on the frame for globals (variables with multi-block lifetime), and
   // one block to share for locals (single-block lifetime).
 
   Context.init(Node);
   Context.setInsertPoint(Context.getCur());
 
+  // If there is a non-deleted InstX86GetIP instruction, we need to move it to
+  // the point after the stack frame has stabilized but before
+  // register-allocated in-args are copied into their home registers.
+  X86Internal::InstX86GetIP<TargetX8632> *GetIPInst = nullptr;
+  if (Ctx->getFlags().getUseNonsfi()) {
+    for (Inst &Instr : Node->getInsts()) {
+      if (auto *GetIP =
+              llvm::dyn_cast<X86Internal::InstX86GetIP<TargetX8632>>(&Instr)) {
+        if (!Instr.isDeleted())
+          GetIPInst = GetIP;
+        break;
+      }
+    }
+  }
+
   llvm::SmallBitVector CalleeSaves =
       getRegisterSet(RegSet_CalleeSave, RegSet_None);
   RegsUsed = llvm::SmallBitVector(CalleeSaves.size());
   VarList SortedSpilledVariables, VariablesLinkedToSpillSlots;
   size_t GlobalsSize = 0;
   // If there is a separate locals area, this represents that area. Otherwise
   // it counts any variable not counted by GlobalsSize.
   SpillAreaSizeBytes = 0;
   // If there is a separate locals area, this specifies the alignment for it.
   uint32_t LocalsSlotsAlignmentBytes = 0;
@@ skipping 121 matching lines @@
 
   // Fill in stack offsets for stack args, and copy args into registers for
   // those that were register-allocated. Args are pushed right to left, so
   // Arg[0] is closest to the stack/frame pointer.
   Variable *FramePtr = getPhysicalRegister(getFrameOrStackReg());
   size_t BasicFrameOffset =
       PreservedRegsSizeBytes + Traits::X86_RET_IP_SIZE_BYTES;
   if (!IsEbpBasedFrame)
     BasicFrameOffset += SpillAreaSizeBytes;
 
+  // Delete any existing InstX86GetIP instruction and reinsert it here.  Also,
+  // insert the call to the helper function and the spill to the stack, to
+  // simplify emission.
+  if (GetIPInst) {
+    GetIPInst->setDeleted();
+    Variable *Dest = GetIPInst->getDest();
+    Variable *CallDest =
+        Dest->hasReg() ? Dest
+                       : getPhysicalRegister(Traits::RegisterSet::Reg_eax);
+    // Call the getIP_<reg> helper.
+    IceString RegName = Traits::getRegName(CallDest->getRegNum());
+    Constant *CallTarget = Ctx->getConstantExternSym(H_getIP_prefix + RegName);
+    Context.insert<Traits::Insts::Call>(CallDest, CallTarget);
+    // Insert a new version of InstX86GetIP.
+    Context.insert<X86Internal::InstX86GetIP<TargetX8632>>(CallDest);
+    // Spill the register to its home stack location if necessary.
+    if (!Dest->hasReg()) {
+      _mov(Dest, CallDest);
+    }
+  }
+
   const VarList &Args = Func->getArgs();
   size_t InArgsSizeBytes = 0;
   unsigned NumXmmArgs = 0;
   for (Variable *Arg : Args) {
     // Skip arguments passed in registers.
     if (isVectorType(Arg->getType()) && NumXmmArgs < Traits::X86_MAX_XMM_ARGS) {
       ++NumXmmArgs;
       continue;
     }
     // For esp-based frames where the allocas are done outside the prolog, the
@@ skipping 120 matching lines @@
     Context.insert<InstFakeUse>(RetValue);
   }
   RI->setDeleted();
 }
 
 void TargetX8632::emitJumpTable(const Cfg *Func,
                                 const InstJumpTable *JumpTable) const {
   if (!BuildDefs::dump())
     return;
   Ostream &Str = Ctx->getStrEmit();
-  IceString MangledName = Ctx->mangleName(Func->getFunctionName());
-  Str << "\t.section\t.rodata." << MangledName
+  const bool UseNonsfi = Ctx->getFlags().getUseNonsfi();
+  const IceString MangledName = Ctx->mangleName(Func->getFunctionName());
+  const IceString Prefix = UseNonsfi ? ".data.rel.ro." : ".rodata.";
+  Str << "\t.section\t" << Prefix << MangledName
       << "$jumptable,\"a\",@progbits\n";
   Str << "\t.align\t" << typeWidthInBytes(getPointerType()) << "\n";
   Str << InstJumpTable::makeName(MangledName, JumpTable->getId()) << ":";
 
   // On X8632 pointers are 32-bit hence the use of .long
   for (SizeT I = 0; I < JumpTable->getNumTargets(); ++I)
     Str << "\n\t.long\t" << JumpTable->getTarget(I)->getAsmName();
   Str << "\n";
 }
 
@@ skipping 138 matching lines @@
     emitConstantPool<PoolTypeConverter<uint16_t>>(Ctx);
     emitConstantPool<PoolTypeConverter<uint32_t>>(Ctx);
 
     emitConstantPool<PoolTypeConverter<float>>(Ctx);
     emitConstantPool<PoolTypeConverter<double>>(Ctx);
   } break;
   }
 }
 
 void TargetDataX8632::lowerJumpTables() {
+  const bool IsPIC = Ctx->getFlags().getUseNonsfi();
   switch (Ctx->getFlags().getOutFileType()) {
   case FT_Elf: {
     ELFObjectWriter *Writer = Ctx->getObjectWriter();
     for (const JumpTableData &JT : Ctx->getJumpTables())
-      Writer->writeJumpTable(JT, TargetX8632::Traits::RelFixup);
+      Writer->writeJumpTable(JT, TargetX8632::Traits::FixupKindAbs, IsPIC);
   } break;
   case FT_Asm:
     // Already emitted from Cfg
     break;
   case FT_Iasm: {
     if (!BuildDefs::dump())
       return;
     Ostream &Str = Ctx->getStrEmit();
+    const IceString Prefix = IsPIC ? ".data.rel.ro." : ".rodata.";
     for (const JumpTableData &JT : Ctx->getJumpTables()) {
-      Str << "\t.section\t.rodata." << JT.getFunctionName()
+      Str << "\t.section\t" << Prefix << JT.getFunctionName()
           << "$jumptable,\"a\",@progbits\n";
       Str << "\t.align\t" << typeWidthInBytes(getPointerType()) << "\n";
       Str << InstJumpTable::makeName(JT.getFunctionName(), JT.getId()) << ":";
 
       // On X8632 pointers are 32-bit hence the use of .long
       for (intptr_t TargetOffset : JT.getTargetOffsets())
         Str << "\n\t.long\t" << JT.getFunctionName() << "+" << TargetOffset;
       Str << "\n";
     }
   } break;
   }
 }
 
 void TargetDataX8632::lowerGlobals(const VariableDeclarationList &Vars,
                                    const IceString &SectionSuffix) {
+  const bool IsPIC = Ctx->getFlags().getUseNonsfi();
   switch (Ctx->getFlags().getOutFileType()) {
   case FT_Elf: {
     ELFObjectWriter *Writer = Ctx->getObjectWriter();
-    Writer->writeDataSection(Vars, TargetX8632::Traits::RelFixup,
-                             SectionSuffix);
+    Writer->writeDataSection(Vars, TargetX8632::Traits::FixupKindAbs,
+                             SectionSuffix, IsPIC);
   } break;
   case FT_Asm:
   case FT_Iasm: {
     const IceString &TranslateOnly = Ctx->getFlags().getTranslateOnly();
     OstreamLocker L(Ctx);
     for (const VariableDeclaration *Var : Vars) {
       if (GlobalContext::matchSymbolName(Var->getName(), TranslateOnly)) {
         emitGlobal(*Var, SectionSuffix);
       }
     }
@@ skipping 102 matching lines @@
 // case the high-level table has extra entries.
 #define X(tag, sizeLog2, align, elts, elty, str)                               \
   static_assert(_table1_##tag == _table2_##tag,                                \
                 "Inconsistency between ICETYPEX8632_TABLE and ICETYPE_TABLE");
 ICETYPE_TABLE
 #undef X
 } // end of namespace dummy3
 } // end of anonymous namespace
 
 } // end of namespace Ice