Subzero: Add Non-SFI support for x86-32.

src/IceInstX86BaseImpl.h

 //===- subzero/src/IceInstX86BaseImpl.h - Generic X86 instructions -*- C++ -*=//
 //
 //                        The Subzero Code Generator
 //
 // This file is distributed under the University of Illinois Open Source
 // License. See LICENSE.TXT for details.
 //
 //===----------------------------------------------------------------------===//
 ///
 /// \file
 /// \brief Implements the InstX86Base class and its descendants.
 ///
 //===----------------------------------------------------------------------===//
 
 #ifndef SUBZERO_SRC_ICEINSTX86BASEIMPL_H
 #define SUBZERO_SRC_ICEINSTX86BASEIMPL_H
 
 #include "IceInstX86Base.h"
 
 #include "IceAssemblerX86Base.h"
 #include "IceCfg.h"
 #include "IceCfgNode.h"
 #include "IceDefs.h"
 #include "IceInst.h"
 #include "IceOperand.h"
 #include "IceTargetLowering.h"
+#include "IceTargetLoweringX86Base.h"
 
 namespace Ice {
 
 namespace X86Internal {
 
 template <class Machine>
 const char *InstX86Base<Machine>::getWidthString(Type Ty) {
   return Traits::TypeAttributes[Ty].WidthString;
 }
 
@@ skipping 13 matching lines @@
                                         InstArithmetic::OpKind Op,
                                         Variable *Beacon)
     : InstX86Base<Machine>(Func, InstX86Base<Machine>::FakeRMW, 3, nullptr),
       Op(Op) {
   this->addSource(Data);
   this->addSource(Addr);
   this->addSource(Beacon);
 }
 
 template <class Machine>
+InstX86GetIP<Machine>::InstX86GetIP(Cfg *Func, Variable *Dest)
+    : InstX86Base<Machine>(Func, InstX86Base<Machine>::GetIP, 0, Dest) {}
+
+template <class Machine>
 InstX86Mul<Machine>::InstX86Mul(Cfg *Func, Variable *Dest, Variable *Source1,
                                 Operand *Source2)
     : InstX86Base<Machine>(Func, InstX86Base<Machine>::Mul, 2, Dest) {
   this->addSource(Source1);
   this->addSource(Source2);
 }
 
 template <class Machine>
 InstX86Shld<Machine>::InstX86Shld(Cfg *Func, Variable *Dest, Variable *Source1,
                                   Operand *Source2)
@@ skipping 317 matching lines @@
   Type Ty = getData()->getType();
   Str << "rmw " << InstArithmetic::getOpName(getOp()) << " " << Ty << " *";
   getAddr()->dump(Func);
   Str << ", ";
   getData()->dump(Func);
   Str << ", beacon=";
   getBeacon()->dump(Func);
 }
 
 template <class Machine>
+void InstX86GetIP<Machine>::emit(const Cfg *Func) const {
+  if (!BuildDefs::dump())
+    return;
+  Ostream &Str = Func->getContext()->getStrEmit();
+  assert(this->getDest()->hasReg());
+  Str << "\t"
+         "addl\t$_GLOBAL_OFFSET_TABLE_, ";
+  this->getDest()->emit(Func);
+}
+
+template <class Machine>
+void InstX86GetIP<Machine>::emitIAS(const Cfg *Func) const {
+  if (Func->getContext()->getFlags().getOutFileType() == FT_Iasm) {
+    // TODO(stichnot): Find a workaround for llvm-mc's inability to handle
+    // something like ".long _GLOBAL_OFFSET_TABLE_ + ." .  One possibility is to
+    // just use hybrid iasm output for this add instruction.
+    llvm::report_fatal_error(
+        "Iasm support for _GLOBAL_OFFSET_TABLE_ not implemented");
+  }
+  typename InstX86Base<Machine>::Traits::Assembler *Asm =
+      Func->getAssembler<typename InstX86Base<Machine>::Traits::Assembler>();
+  assert(this->getDest()->hasReg());
+  typename InstX86Base<Machine>::Traits::GPRRegister Reg =
+      InstX86Base<Machine>::Traits::getEncodedGPR(this->getDest()->getRegNum());
+  Constant *GlobalOffsetTable =
+      Func->getContext()->getConstantExternSym("_GLOBAL_OFFSET_TABLE_");
+  AssemblerFixup *Fixup = Asm->createFixup(
+      InstX86Base<Machine>::Traits::FixupKindGotPC, GlobalOffsetTable);
+  intptr_t OrigPos = Asm->getBufferSize();
+  constexpr int32_t TempDisp = 0;
+  constexpr int32_t ImmediateWidth = 4;
+  // Emit the add instruction once, in a preliminary fashion, to find its total
+  // size.
+  Asm->add(IceType_i32, Reg, Immediate(TempDisp, Fixup));

[John, 2015/12/22 15:44:38]

I believe the assembler will always emit an addl imm32, %reg here because it
can't possibly know how small the immediate can be.

[Jim Stichnoth, 2015/12/28 07:54:07]

Right, but the specific issue here is that adding to eax takes 5 bytes while
adding to other registers takes 6 bytes.

+  const int32_t Disp = Asm->getBufferSize() - OrigPos - ImmediateWidth;
+  // Now roll back and emit the add instruction again, this time with the
+  // correct displacement.
+  Asm->setBufferSize(OrigPos);
+  Asm->add(IceType_i32, Reg, Immediate(Disp, Fixup));
+}
+
+template <class Machine>
+void InstX86GetIP<Machine>::dump(const Cfg *Func) const {
+  if (!BuildDefs::dump())
+    return;
+  Ostream &Str = Func->getContext()->getStrDump();
+  this->getDest()->dump(Func);
+  Str << " = call getIP";
+}
+
+template <class Machine>
 void InstX86Label<Machine>::emit(const Cfg *Func) const {
   if (!BuildDefs::dump())
     return;
   Ostream &Str = Func->getContext()->getStrEmit();
   Str << getName(Func) << ":";
 }
 
 template <class Machine>
 void InstX86Label<Machine>::emitIAS(const Cfg *Func) const {
   typename InstX86Base<Machine>::Traits::Assembler *Asm =
@@ skipping 288 matching lines @@
       (Asm->*(Emitter.GPRAddr))(Ty, VarReg, SrcStackAddr);
     }
   } else if (const auto *Mem = llvm::dyn_cast<
                  typename InstX86Base<Machine>::Traits::X86OperandMem>(Src)) {
     Mem->emitSegmentOverride(Asm);
     (Asm->*(Emitter.GPRAddr))(Ty, VarReg, Mem->toAsmAddress(Asm, Target));
   } else if (const auto *Imm = llvm::dyn_cast<ConstantInteger32>(Src)) {
     (Asm->*(Emitter.GPRImm))(Ty, VarReg, Immediate(Imm->getValue()));
   } else if (const auto *Reloc = llvm::dyn_cast<ConstantRelocatable>(Src)) {
     AssemblerFixup *Fixup =
-        Asm->createFixup(InstX86Base<Machine>::Traits::RelFixup, Reloc);
+        Asm->createFixup(TargetX86Base<Machine>::getRelFixup(), Reloc);
     (Asm->*(Emitter.GPRImm))(Ty, VarReg, Immediate(Reloc->getOffset(), Fixup));
   } else if (const auto *Split = llvm::dyn_cast<
                  typename InstX86Base<Machine>::Traits::VariableSplit>(Src)) {
     (Asm->*(Emitter.GPRAddr))(Ty, VarReg, Split->toAsmAddress(Func));
   } else {
     llvm_unreachable("Unexpected operand type");
   }
 }
 
 template <class Machine>
 void emitIASAddrOpTyGPR(
     const Cfg *Func, Type Ty,
     const typename InstX86Base<Machine>::Traits::Address &Addr,
     const Operand *Src,
     const typename InstX86Base<Machine>::Traits::Assembler::GPREmitterAddrOp
         &Emitter) {
   typename InstX86Base<Machine>::Traits::Assembler *Asm =
       Func->getAssembler<typename InstX86Base<Machine>::Traits::Assembler>();
   // Src can only be Reg or Immediate.
   if (const auto *SrcVar = llvm::dyn_cast<Variable>(Src)) {
     assert(SrcVar->hasReg());
     typename InstX86Base<Machine>::Traits::RegisterSet::GPRRegister SrcReg =
         InstX86Base<Machine>::Traits::getEncodedGPR(SrcVar->getRegNum());
     (Asm->*(Emitter.AddrGPR))(Ty, Addr, SrcReg);
   } else if (const auto *Imm = llvm::dyn_cast<ConstantInteger32>(Src)) {
     (Asm->*(Emitter.AddrImm))(Ty, Addr, Immediate(Imm->getValue()));
   } else if (const auto *Reloc = llvm::dyn_cast<ConstantRelocatable>(Src)) {
     AssemblerFixup *Fixup =
-        Asm->createFixup(InstX86Base<Machine>::Traits::RelFixup, Reloc);
+        Asm->createFixup(TargetX86Base<Machine>::getRelFixup(), Reloc);
     (Asm->*(Emitter.AddrImm))(Ty, Addr, Immediate(Reloc->getOffset(), Fixup));
   } else {
     llvm_unreachable("Unexpected operand type");
   }
 }
 
 template <class Machine>
 void emitIASAsAddrOpTyGPR(
     const Cfg *Func, Type Ty, const Operand *Op0, const Operand *Op1,
     const typename InstX86Base<Machine>::Traits::Assembler::GPREmitterAddrOp
@@ skipping 2276 matching lines @@
     return;
   Ostream &Str = Func->getContext()->getStrDump();
   Str << "IACA_END";
 }
 
 } // end of namespace X86Internal
 
 } // end of namespace Ice
 
 #endif // SUBZERO_SRC_ICEINSTX86BASEIMPL_H