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Side by Side Diff: runtime/vm/simulator_mips.cc

Issue 15038008: Impelemnts some FPU arithmetic function for the MIPS simulator, assembler, disassembler. (Closed) Base URL: http://dart.googlecode.com/svn/branches/bleeding_edge/dart/
Patch Set: Created 7 years, 7 months ago
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1 // Copyright (c) 2013, the Dart project authors. Please see the AUTHORS file 1 // Copyright (c) 2013, the Dart project authors. Please see the AUTHORS file
2 // for details. All rights reserved. Use of this source code is governed by a 2 // for details. All rights reserved. Use of this source code is governed by a
3 // BSD-style license that can be found in the LICENSE file. 3 // BSD-style license that can be found in the LICENSE file.
4 4
5 #include <math.h> // for isnan. 5 #include <math.h> // for isnan.
6 #include <setjmp.h> 6 #include <setjmp.h>
7 #include <stdlib.h> 7 #include <stdlib.h>
8 8
9 #include "vm/globals.h" 9 #include "vm/globals.h"
10 #if defined(TARGET_ARCH_MIPS) 10 #if defined(TARGET_ARCH_MIPS)
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1381 uint32_t cc, fcsr_cc; 1381 uint32_t cc, fcsr_cc;
1382 cc = instr->FpuCCField(); 1382 cc = instr->FpuCCField();
1383 fcsr_cc = get_fcsr_condition_bit(cc); 1383 fcsr_cc = get_fcsr_condition_bit(cc);
1384 switch (instr->Cop1FunctionField()) { 1384 switch (instr->Cop1FunctionField()) {
1385 case COP1_ADD: { 1385 case COP1_ADD: {
1386 // Format(instr, "add.'fmt 'fd, 'fs, 'ft"); 1386 // Format(instr, "add.'fmt 'fd, 'fs, 'ft");
1387 ASSERT(instr->FormatField() == FMT_D); // Only D supported. 1387 ASSERT(instr->FormatField() == FMT_D); // Only D supported.
1388 set_fregister_double(instr->FdField(), fs_val + ft_val); 1388 set_fregister_double(instr->FdField(), fs_val + ft_val);
1389 break; 1389 break;
1390 } 1390 }
1391 case COP1_SUB: {
1392 // Format(instr, "sub.'fmt 'fd, 'fs, 'ft");
1393 ASSERT(instr->FormatField() == FMT_D); // Only D supported.
1394 set_fregister_double(instr->FdField(), fs_val - ft_val);
1395 break;
1396 }
1397 case COP1_MUL: {
1398 // Format(instr, "mul.'fmt 'fd, 'fs, 'ft");
1399 ASSERT(instr->FormatField() == FMT_D); // Only D supported.
1400 set_fregister_double(instr->FdField(), fs_val * ft_val);
1401 break;
1402 }
1403 case COP1_DIV: {
1404 // Format(instr, "div.'fmt 'fd, 'fs, 'ft");
1405 ASSERT(instr->FormatField() == FMT_D); // Only D supported.
1406 set_fregister_double(instr->FdField(), fs_val / ft_val);
1407 break;
1408 }
1409 case COP1_SQRT: {
1410 // Format(instr, "sqrt.'fmt 'fd, 'fs");
1411 ASSERT(instr->FormatField() == FMT_D); // Only D supported.
1412 set_fregister_double(instr->FdField(), sqrt(fs_val));
1413 break;
1414 }
1391 case COP1_MOV: { 1415 case COP1_MOV: {
1392 // Format(instr, "mov.'fmt 'fd, 'fs"); 1416 // Format(instr, "mov.'fmt 'fd, 'fs");
1393 ASSERT(instr->FormatField() == FMT_D); // Only D supported. 1417 ASSERT(instr->FormatField() == FMT_D); // Only D supported.
1394 set_fregister_double(instr->FdField(), fs_val); 1418 set_fregister_double(instr->FdField(), fs_val);
1395 break; 1419 break;
1396 } 1420 }
1397 case COP1_C_F: { 1421 case COP1_C_F: {
1398 ASSERT(instr->FormatField() == FMT_D); // Only D supported. 1422 ASSERT(instr->FormatField() == FMT_D); // Only D supported.
1399 ASSERT(instr->FdField() == F0); 1423 ASSERT(instr->FdField() == F0);
1400 set_fcsr_bit(fcsr_cc, false); 1424 set_fcsr_bit(fcsr_cc, false);
(...skipping 59 matching lines...) Expand 10 before | Expand all | Expand 10 after
1460 break; 1484 break;
1461 } 1485 }
1462 default: { 1486 default: {
1463 OS::PrintErr("DecodeCop1: 0x%x\n", instr->InstructionBits()); 1487 OS::PrintErr("DecodeCop1: 0x%x\n", instr->InstructionBits());
1464 UnimplementedInstruction(instr); 1488 UnimplementedInstruction(instr);
1465 break; 1489 break;
1466 } 1490 }
1467 } 1491 }
1468 break; 1492 break;
1469 } 1493 }
1494 case COP1_CVT_W: {
1495 switch (instr->FormatField()) {
1496 case FMT_D: {
1497 double fs_dbl = get_fregister_double(instr->FsField());
1498 int32_t fs_int = static_cast<int32_t>(fs_dbl);
1499 set_fregister(instr->FdField(), fs_int);
1500 break;
1501 }
1502 default: {
1503 OS::PrintErr("DecodeCop1: 0x%x\n", instr->InstructionBits());
1504 UnimplementedInstruction(instr);
1505 break;
1506 }
1507 }
1508 break;
1509 }
1470 default: { 1510 default: {
1471 OS::PrintErr("DecodeCop1: 0x%x\n", instr->InstructionBits()); 1511 OS::PrintErr("DecodeCop1: 0x%x\n", instr->InstructionBits());
1472 UnimplementedInstruction(instr); 1512 UnimplementedInstruction(instr);
1473 break; 1513 break;
1474 } 1514 }
1475 } 1515 }
1476 } else { 1516 } else {
1477 // If the rs field isn't a valid format, then it must be a sub-op. 1517 // If the rs field isn't a valid format, then it must be a sub-op.
1478 switch (instr->Cop1SubField()) { 1518 switch (instr->Cop1SubField()) {
1479 case COP1_MF: { 1519 case COP1_MF: {
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1955 set_register(kStackTraceObjectReg, bit_cast<int32_t>(raw_stacktrace)); 1995 set_register(kStackTraceObjectReg, bit_cast<int32_t>(raw_stacktrace));
1956 } 1996 }
1957 buf->Longjmp(); 1997 buf->Longjmp();
1958 } 1998 }
1959 1999
1960 } // namespace dart 2000 } // namespace dart
1961 2001
1962 #endif // !defined(HOST_ARCH_MIPS) 2002 #endif // !defined(HOST_ARCH_MIPS)
1963 2003
1964 #endif // defined TARGET_ARCH_MIPS 2004 #endif // defined TARGET_ARCH_MIPS
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