Impelemnts some FPU arithmetic function for the MIPS simulator, assembler, disassembler.

runtime/vm/assembler_mips.h

 // Copyright (c) 2013, the Dart project authors.  Please see the AUTHORS file
 // for details. All rights reserved. Use of this source code is governed by a
 // BSD-style license that can be found in the LICENSE file.
 
 #ifndef VM_ASSEMBLER_MIPS_H_
 #define VM_ASSEMBLER_MIPS_H_
 
 #ifndef VM_ASSEMBLER_H_
 #error Do not include assembler_mips.h directly; use assembler.h instead.
 #endif
@@ skipping 436 matching lines @@
     EmitFpuRType(COP1, FMT_W, F0, fs, fd, COP1_CVT_D);
   }
 
   // Converts a 64-bit signed int in fs to a double in fd.
   void cvtdl(FRegister fd, FRegister fs) {
     ASSERT(EvenFPURegister(fs));
     ASSERT(EvenFPURegister(fd));
     EmitFpuRType(COP1, FMT_L, F0, fs, fd, COP1_CVT_D);
   }
 
+  void cvtwd(FRegister fd, FRegister fs) {
+    ASSERT(EvenFPURegister(fs));
+    ASSERT(EvenFPURegister(fd));
+    EmitFpuRType(COP1, FMT_D, F0, fs, fd, COP1_CVT_W);
+  }
+
   void div(Register rs, Register rt) {
     EmitRType(SPECIAL, rs, rt, R0, 0, DIV);
   }
 
+  void divd(FRegister fd, FRegister fs, FRegister ft) {
+    ASSERT(EvenFPURegister(fd));
+    ASSERT(EvenFPURegister(fs));
+    ASSERT(EvenFPURegister(ft));
+    EmitFpuRType(COP1, FMT_D, ft, fs, fd, COP1_DIV);
+  }
+
   void divu(Register rs, Register rt) {
     EmitRType(SPECIAL, rs, rt, R0, 0, DIVU);
   }
 
   void jalr(Register rs, Register rd = RA) {
     ASSERT(rs != rd);
     ASSERT(!in_delay_slot_);  // Jump within a delay slot is not supported.
     EmitRType(SPECIAL, rs, R0, rd, 0, JALR);
     EmitBranchDelayNop();
   }
@@ skipping 76 matching lines @@
     EmitFpuRType(COP1, FMT_S, F0, fs, fd, COP1_MOV);
   }
 
   void mtc1(Register rt, FRegister fs) {
     Emit(COP1 << kOpcodeShift |
          COP1_MT << kCop1SubShift |
          rt << kRtShift |
          fs << kFsShift);
   }
 
+  void muld(FRegister fd, FRegister fs, FRegister ft) {
+    ASSERT(EvenFPURegister(fd));
+    ASSERT(EvenFPURegister(fs));
+    ASSERT(EvenFPURegister(ft));
+    EmitFpuRType(COP1, FMT_D, ft, fs, fd, COP1_MUL);
+  }
+
   void mult(Register rs, Register rt) {
     EmitRType(SPECIAL, rs, rt, R0, 0, MULT);
   }
 
   void multu(Register rs, Register rt) {
     EmitRType(SPECIAL, rs, rt, R0, 0, MULTU);
   }
 
   void nop() {
     Emit(Instr::kNopInstruction);
@@ skipping 35 matching lines @@
   }
 
   void slt(Register rd, Register rs, Register rt) {
     EmitRType(SPECIAL, rs, rt, rd, 0, SLT);
   }
 
   void sltu(Register rd, Register rs, Register rt) {
     EmitRType(SPECIAL, rs, rt, rd, 0, SLTU);
   }
 
+  void sqrtd(FRegister fd, FRegister fs) {
+    ASSERT(EvenFPURegister(fd));
+    ASSERT(EvenFPURegister(fs));
+    EmitFpuRType(COP1, FMT_D, F0, fs, fd, COP1_SQRT);
+  }
+
   void sra(Register rd, Register rt, int sa) {
     EmitRType(SPECIAL, R0, rt, rd, sa, SRA);
   }
 
   void srav(Register rd, Register rt, Register rs) {
     EmitRType(SPECIAL, rs, rt, rd, 0, SRAV);
   }
 
   void srl(Register rd, Register rt, int sa) {
     EmitRType(SPECIAL, R0, rt, rd, sa, SRL);
   }
 
   void srlv(Register rd, Register rt, Register rs) {
     EmitRType(SPECIAL, rs, rt, rd, 0, SRLV);
   }
 
+  void subd(FRegister fd, FRegister fs, FRegister ft) {
+    ASSERT(EvenFPURegister(fd));
+    ASSERT(EvenFPURegister(fs));
+    ASSERT(EvenFPURegister(ft));
+    EmitFpuRType(COP1, FMT_D, ft, fs, fd, COP1_SUB);
+  }
+
   void subu(Register rd, Register rs, Register rt) {
     EmitRType(SPECIAL, rs, rt, rd, 0, SUBU);
   }
 
   void sw(Register rt, const Address& addr) {
     EmitLoadStore(SW, rt, addr);
   }
 
   void swc1(FRegister ft, const Address& addr) {
     EmitFpuLoadStore(SWC1, ft, addr);
@@ skipping 470 matching lines @@
                                   Register value,
                                   Label* no_update);
 
   DISALLOW_ALLOCATION();
   DISALLOW_COPY_AND_ASSIGN(Assembler);
 };
 
 }  // namespace dart
 
 #endif  // VM_ASSEMBLER_MIPS_H_