Add Sxtb instructions to ARM integrated assembler.

src/IceAssemblerARM32.cpp

 //===- subzero/src/IceAssemblerARM32.cpp - Assembler for ARM32 --*- C++ -*-===//
 //
 // Copyright (c) 2013, the Dart project authors.  Please see the AUTHORS file
 // for details. All rights reserved. Use of this source code is governed by a
 // BSD-style license that can be found in the LICENSE file.
 //
 // Modified by the Subzero authors.
 //
 //===----------------------------------------------------------------------===//
 //
@@ skipping 817 matching lines @@
   verifyRegDefined(Rs, "Rs", InstName);
   verifyCondDefined(Cond, InstName);
   AssemblerBuffer::EnsureCapacity ensured(&Buffer);
   IValueT Encoding = Opcode | (encodeCondition(Cond) << kConditionShift) |
                      (encodeBool(SetFlags) << kSShift) | (Rn << kRnShift) |
                      (Rd << kRdShift) | (Rs << kRsShift) | B7 | B4 |
                      (Rm << kRmShift);
   emitInst(Encoding);
 }
 
-void AssemblerARM32::emitUxt(CondARM32::Cond Cond, IValueT Opcode, IValueT Rd,
-                             IValueT Rn, IValueT Rm, RotationValue Rotation,
-                             const char *InstName) {
-  verifyCondDefined(Cond, InstName);
-  IValueT Rot = encodeRotation(Rotation);
-  if (!Utils::IsUint(2, Rot))
-    llvm::report_fatal_error(std::string(InstName) +
-                             ": Illegal rotation value");
-  AssemblerBuffer::EnsureCapacity ensured(&Buffer);
-  IValueT Encoding = (encodeCondition(Cond) << kConditionShift) | Opcode |
-                     (Rn << kRnShift) | (Rd << kRdShift) |
-                     (Rot << kRotationShift) | B6 | B5 | B4 | (Rm << kRmShift);
-  emitInst(Encoding);
-}
-
 void AssemblerARM32::emitMultiMemOp(CondARM32::Cond Cond,
                                     BlockAddressMode AddressMode, bool IsLoad,
                                     IValueT BaseReg, IValueT Registers,
                                     const char *InstName) {
   constexpr IValueT NumGPRegisters = 16;
   verifyCondDefined(Cond, InstName);
   verifyRegDefined(BaseReg, "base", InstName);
   if (Registers >= (1 << NumGPRegisters))
     llvm::report_fatal_error(std::string(InstName) +
                              ": Register set too large");
   AssemblerBuffer::EnsureCapacity ensured(&Buffer);
   IValueT Encoding = (encodeCondition(Cond) << kConditionShift) | B27 |
                      AddressMode | (IsLoad ? L : 0) | (BaseReg << kRnShift) |
                      Registers;
   emitInst(Encoding);
 }
 
+void AssemblerARM32::emitSignExtend(CondARM32::Cond Cond, IValueT Opcode,
+                                    const Operand *OpRd, const Operand *OpSrc0,
+                                    const char *InstName) {
+  IValueT Rd = encodeRegister(OpRd, "Rd", InstName);
+  IValueT Rm = encodeRegister(OpSrc0, "Rm", InstName);
+  // Note: For the moment, we assume no rotation is specified.
+  RotationValue Rotation = kRotateNone;
+  constexpr IValueT Rn = RegARM32::Encoded_Reg_pc;
+  switch (typeWidthInBytes(OpSrc0->getType())) {
+  default:
+    llvm::report_fatal_error(std::string(InstName) +
+                             ": Type of Rm not understood");
+    break;
+  case 1: {
+    // SXTB/UXTB - Arm sections A8.8.233 and A8.8.274, encoding A1:
+    //   sxtb<c> <Rd>, <Rm>{, <rotate>}
+    //   uxtb<c> <Rd>, <Rm>{, <rotate>}
+    //
+    // ccccxxxxxxxx1111ddddrr000111mmmm where cccc=Cond, xxxxxxxx<<20=Opcode,
+    // dddd=Rd, mmmm=Rm, and rr defined (RotationValue) rotate.
+    break;
+  }
+  case 2: {
+    // SXTH/UXTH - ARM sections A8.8.235 and A8.8.276, encoding A1:
+    //   uxth<c> <Rd>< <Rm>{, <rotate>}
+    //
+    // cccc01101111nnnnddddrr000111mmmm where cccc=Cond, dddd=Rd, mmmm=Rm, and
+    // rr defined (RotationValue) rotate.
+    Opcode |= B20;
+    break;
+  }
+  }
+
+  verifyCondDefined(Cond, InstName);
+  IValueT Rot = encodeRotation(Rotation);
+  if (!Utils::IsUint(2, Rot))
+    llvm::report_fatal_error(std::string(InstName) +
+                             ": Illegal rotation value");
+  AssemblerBuffer::EnsureCapacity ensured(&Buffer);
+  IValueT Encoding = (encodeCondition(Cond) << kConditionShift) | Opcode |
+                     (Rn << kRnShift) | (Rd << kRdShift) |
+                     (Rot << kRotationShift) | B6 | B5 | B4 | (Rm << kRmShift);
+  emitInst(Encoding);
+}
+
 void AssemblerARM32::adc(const Operand *OpRd, const Operand *OpRn,
                          const Operand *OpSrc1, bool SetFlags,
                          CondARM32::Cond Cond) {
   // ADC (register) - ARM section 18.8.2, encoding A1:
   //   adc{s}<c> <Rd>, <Rn>, <Rm>{, <shift>}
   //
   // cccc0000101snnnnddddiiiiitt0mmmm where cccc=Cond, dddd=Rd, nnnn=Rn,
   // mmmm=Rm, iiiii=Shift, tt=ShiftKind, and s=SetFlags.
   //
   // ADC (Immediate) - ARM section A8.8.1, encoding A1:
@@ skipping 623 matching lines @@
   //   rsb{s}<c> <Rd>, <Rn>, <Rm>{, <Shift>}
   //
   // cccc0000011snnnnddddiiiiitt0mmmm where cccc=Cond, dddd=Rd, nnnn=Rn,
   // mmmm=Rm, iiiii=shift, tt==ShiftKind, and s=SetFlags.
   constexpr const char *RsbName = "rsb";
   constexpr IValueT RsbOpcode = B1 | B0; // 0011
   emitType01(Cond, RsbOpcode, OpRd, OpRn, OpSrc1, SetFlags, RdIsPcAndSetFlags,
              RsbName);
 }
 
+void AssemblerARM32::sxt(const Operand *OpRd, const Operand *OpSrc0,
+                         CondARM32::Cond Cond) {
+  constexpr const char *SxtName = "sxt";
+  constexpr IValueT SxtOpcode = B26 | B25 | B23 | B21;
+  emitSignExtend(Cond, SxtOpcode, OpRd, OpSrc0, SxtName);
+}
+
 void AssemblerARM32::sub(const Operand *OpRd, const Operand *OpRn,
                          const Operand *OpSrc1, bool SetFlags,
                          CondARM32::Cond Cond) {
   // SUB (register) - ARM section A8.8.223, encoding A1:
   //   sub{s}<c> <Rd>, <Rn>, <Rm>{, <shift>}
   // SUB (SP minus register): See ARM section 8.8.226, encoding A1:
   //   sub{s}<c> <Rd>, sp, <Rm>{, <Shift>}
   //
   // cccc0000010snnnnddddiiiiitt0mmmm where cccc=Cond, dddd=Rd, nnnn=Rn,
   // mmmm=Rm, iiiii=shift, tt=ShiftKind, and s=SetFlags.
@@ skipping 67 matching lines @@
   verifyRegNotPc(Rm, "Rm", UmullName);
   verifyRegsNotEq(RdHi, "RdHi", RdLo, "RdLo", UmullName);
   constexpr IValueT UmullOpcode = B23;
   constexpr bool SetFlags = false;
   emitMulOp(Cond, UmullOpcode, RdLo, RdHi, Rn, Rm, SetFlags, UmullName);
 }
 
 void AssemblerARM32::uxt(const Operand *OpRd, const Operand *OpSrc0,
                          CondARM32::Cond Cond) {
   constexpr const char *UxtName = "uxt";
-  IValueT Rd = encodeRegister(OpRd, "Rd", UxtName);
-  IValueT Rm = encodeRegister(OpSrc0, "Rm", UxtName);
-  // Note: For the moment, we assume no rotation is specified.
-  RotationValue Rotation = kRotateNone;
-  constexpr IValueT Rn = RegARM32::Encoded_Reg_pc;
-  switch (typeWidthInBytes(OpSrc0->getType())) {
-  default:
-    llvm::report_fatal_error("Type of Rm not understood: uxt");
-  case 1: {
-    // UXTB - ARM section A8.8.274, encoding A1:
-    //   uxtb<c> <Rd>, <Rm>{, <rotate>}
-    //
-    // cccc011011101111ddddrr000111mmmm where cccc=Cond, dddd=Rd, mmmm=Rm, and
-    // rr defined (RotationValue) rotate.
-    constexpr IValueT UxtOpcode = B26 | B25 | B23 | B22 | B21;
-    emitUxt(Cond, UxtOpcode, Rd, Rn, Rm, Rotation, UxtName);
-    return;
-  }
-  case 2: {
-    // UXTH - ARM section A8.8.276, encoding A1:
-    //   uxth<c> <Rd>< <Rm>{, <rotate>}
-    //
-    // cccc01101111nnnnddddrr000111mmmm where cccc=Cond, dddd=Rd, mmmm=Rm, and
-    // rr defined (RotationValue) rotate.
-    constexpr IValueT UxtOpcode = B26 | B25 | B23 | B22 | B21 | B20;
-    emitUxt(Cond, UxtOpcode, Rd, Rn, Rm, Rotation, UxtName);
-    return;
-  }
-  }
+  constexpr IValueT UxtOpcode = B26 | B25 | B23 | B22 | B21;
+  emitSignExtend(Cond, UxtOpcode, OpRd, OpSrc0, UxtName);
 }
 
 } // end of namespace ARM32
 } // end of namespace Ice