Add Sxtb instructions to ARM integrated assembler.

src/IceAssemblerARM32.h

 //===- subzero/src/IceAssemblerARM32.h - Assembler for ARM32 ----*- C++ -*-===//
 //
 // Copyright (c) 2013, the Dart project authors.  Please see the AUTHORS file
 // for details. All rights reserved. Use of this source code is governed by a
 // BSD-style license that can be found in the LICENSE file.
 //
 // Modified by the Subzero authors.
 //
 //===----------------------------------------------------------------------===//
 //
@@ skipping 255 matching lines @@
 
   void str(const Operand *OpRt, const Operand *OpAddress, CondARM32::Cond Cond,
            const TargetLowering *Lowering) {
     const TargetInfo TInfo(Lowering);
     str(OpRt, OpAddress, Cond, TInfo);
   }
 
   void sub(const Operand *OpRd, const Operand *OpRn, const Operand *OpSrc1,
            bool SetFlags, CondARM32::Cond Cond);
 
+  // Implements sxtb/sxth depending on type of OpSrc0.
+  void sxt(const Operand *OpRd, const Operand *OpSrc0, CondARM32::Cond Cond);
+
   void tst(const Operand *OpRn, const Operand *OpSrc1, CondARM32::Cond Cond);
 
   void udiv(const Operand *OpRd, const Operand *OpRn, const Operand *OpSrc1,
             CondARM32::Cond Cond);
 
   void umull(const Operand *OpRdLo, const Operand *OpRdHi, const Operand *OpRn,
              const Operand *OpRm, CondARM32::Cond Cond);
 
   // Implements uxtb/uxth depending on type of OpSrc0.
   void uxt(const Operand *OpRd, const Operand *OpSrc0, CondARM32::Cond Cond);
@@ skipping 94 matching lines @@
                  IValueT Rm, IValueT Rs, bool SetFlags, const char *InstName);
 
   // Pattern cccc0001101s0000ddddxxxxxtt0mmmm where cccc=Cond, s=SetFlags,
   // dddd=Rd, mmmm=Rm, tt=Shift, and xxxxx is defined by OpSrc1. OpSrc1 defines
   // either xxxxx=Imm5, or xxxxx=ssss0 where ssss=Rs.
   void emitShift(const CondARM32::Cond Cond,
                  const OperandARM32::ShiftKind Shift, const Operand *OpRd,
                  const Operand *OpRm, const Operand *OpSrc1,
                  const bool SetFlags, const char *InstName);
 
-  // Implements various forms of Unsigned extend value, using pattern
+  // Implements various forms of signed/unsigned extend value, using pattern
   // ccccxxxxxxxxnnnnddddrr000111mmmm where cccc=Cond, xxxxxxxx<<20=Opcode,
   // nnnn=Rn, dddd=Rd, rr=Rotation, and mmmm=Rm.
-  void emitUxt(CondARM32::Cond, IValueT Opcode, IValueT Rd, IValueT Rn,
-               IValueT Rm, RotationValue Rotation, const char *InstName);
+  void emitSignExtend(CondARM32::Cond, IValueT Opcode, const Operand *OpRd,
+                      const Operand *OpSrc0, const char *InstName);
 
   // Pattern cccctttxxxxnnnn0000iiiiiiiiiiii where cccc=Cond, nnnn=Rn,
   // ttt=Instruction type (derived from OpSrc1), iiiiiiiiiiii is derived from
   // OpSrc1, and xxxx=Opcode.
   void emitCompareOp(CondARM32::Cond Cond, IValueT Opcode, const Operand *OpRn,
                      const Operand *OpSrc1, const char *CmpName);
 
   void emitBranch(Label *L, CondARM32::Cond, bool Link);
 
   // Encodes the given Offset into the branch instruction Inst.
   IValueT encodeBranchOffset(IOffsetT Offset, IValueT Inst);
 
   // Returns the offset encoded in the branch instruction Inst.
   static IOffsetT decodeBranchOffset(IValueT Inst);
 
   // Implements movw/movt, generating pattern ccccxxxxxxxsiiiiddddiiiiiiiiiiii
   // where cccc=Cond, xxxxxxx<<21=Opcode, dddd=Rd, s=SetFlags, and
   // iiiiiiiiiiiiiiii=Imm16.
   void emitMovwt(CondARM32::Cond Cond, bool IsMovw, const Operand *OpRd,
                  const Operand *OpSrc, const char *MovName);
 };
 
 } // end of namespace ARM32
 } // end of namespace Ice
 
 #endif // SUBZERO_SRC_ICEASSEMBLERARM32_H