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Issue 1501073002: Implement LSR instructions for the integrated ARM assembler. (Closed) Base URL: https://chromium.googlesource.com/native_client/pnacl-subzero.git@master
Patch Set: Fix nit. Created 5 years ago
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1 // Copyright (c) 2013, the Dart project authors. Please see the AUTHORS file 1 // Copyright (c) 2013, the Dart project authors. Please see the AUTHORS file
2 // for details. All rights reserved. Use of this source code is governed by a 2 // for details. All rights reserved. Use of this source code is governed by a
3 // BSD-style license that can be found in the LICENSE file. 3 // BSD-style license that can be found in the LICENSE file.
4 // 4 //
5 // This is forked from Dart revision df52deea9f25690eb8b66c5995da92b70f7ac1fe 5 // This is forked from Dart revision df52deea9f25690eb8b66c5995da92b70f7ac1fe
6 // Please update the (git) revision if we merge changes from Dart. 6 // Please update the (git) revision if we merge changes from Dart.
7 // https://code.google.com/p/dart/wiki/GettingTheSource 7 // https://code.google.com/p/dart/wiki/GettingTheSource
8 8
9 #include "vm/globals.h" // NOLINT 9 #include "vm/globals.h" // NOLINT
10 #if defined(TARGET_ARCH_ARM) 10 #if defined(TARGET_ARCH_ARM)
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2596 Condition cond) { 2596 Condition cond) {
2597 ASSERT(shift_imm.type() == 1); 2597 ASSERT(shift_imm.type() == 1);
2598 ASSERT(shift_imm.encoding() != 0); // Do not use Lsl if no shift is wanted. 2598 ASSERT(shift_imm.encoding() != 0); // Do not use Lsl if no shift is wanted.
2599 mov(rd, Operand(rm, LSL, shift_imm.encoding()), cond); 2599 mov(rd, Operand(rm, LSL, shift_imm.encoding()), cond);
2600 } 2600 }
2601 2601
2602 // Moved to ARM32::AssemblerARM32::lsl() 2602 // Moved to ARM32::AssemblerARM32::lsl()
2603 void Assembler::Lsl(Register rd, Register rm, Register rs, Condition cond) { 2603 void Assembler::Lsl(Register rd, Register rm, Register rs, Condition cond) {
2604 mov(rd, Operand(rm, LSL, rs), cond); 2604 mov(rd, Operand(rm, LSL, rs), cond);
2605 } 2605 }
2606 #endif
2607 2606
2607 // Moved to ARM32::AssemblerARM32::lsr()
2608 void Assembler::Lsr(Register rd, Register rm, const Operand& shift_imm, 2608 void Assembler::Lsr(Register rd, Register rm, const Operand& shift_imm,
2609 Condition cond) { 2609 Condition cond) {
2610 ASSERT(shift_imm.type() == 1); 2610 ASSERT(shift_imm.type() == 1);
2611 uint32_t shift = shift_imm.encoding(); 2611 uint32_t shift = shift_imm.encoding();
2612 ASSERT(shift != 0); // Do not use Lsr if no shift is wanted. 2612 ASSERT(shift != 0); // Do not use Lsr if no shift is wanted.
2613 if (shift == 32) { 2613 if (shift == 32) {
2614 shift = 0; // Comply to UAL syntax. 2614 shift = 0; // Comply to UAL syntax.
2615 } 2615 }
2616 mov(rd, Operand(rm, LSR, shift), cond); 2616 mov(rd, Operand(rm, LSR, shift), cond);
2617 } 2617 }
2618 2618
2619 2619 // Moved to ARM32::AssemblerARM32::lsr()
2620 void Assembler::Lsr(Register rd, Register rm, Register rs, Condition cond) { 2620 void Assembler::Lsr(Register rd, Register rm, Register rs, Condition cond) {
2621 mov(rd, Operand(rm, LSR, rs), cond); 2621 mov(rd, Operand(rm, LSR, rs), cond);
2622 } 2622 }
2623 #endif
2623 2624
2624 2625
2625 void Assembler::Asr(Register rd, Register rm, const Operand& shift_imm, 2626 void Assembler::Asr(Register rd, Register rm, const Operand& shift_imm,
2626 Condition cond) { 2627 Condition cond) {
2627 ASSERT(shift_imm.type() == 1); 2628 ASSERT(shift_imm.type() == 1);
2628 uint32_t shift = shift_imm.encoding(); 2629 uint32_t shift = shift_imm.encoding();
2629 ASSERT(shift != 0); // Do not use Asr if no shift is wanted. 2630 ASSERT(shift != 0); // Do not use Asr if no shift is wanted.
2630 if (shift == 32) { 2631 if (shift == 32) {
2631 shift = 0; // Comply to UAL syntax. 2632 shift = 0; // Comply to UAL syntax.
2632 } 2633 }
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3686 3687
3687 3688
3688 const char* Assembler::FpuRegisterName(FpuRegister reg) { 3689 const char* Assembler::FpuRegisterName(FpuRegister reg) {
3689 ASSERT((0 <= reg) && (reg < kNumberOfFpuRegisters)); 3690 ASSERT((0 <= reg) && (reg < kNumberOfFpuRegisters));
3690 return fpu_reg_names[reg]; 3691 return fpu_reg_names[reg];
3691 } 3692 }
3692 3693
3693 } // namespace dart 3694 } // namespace dart
3694 3695
3695 #endif // defined TARGET_ARCH_ARM 3696 #endif // defined TARGET_ARCH_ARM
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