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| 1 // Copyright (c) 2013, the Dart project authors. Please see the AUTHORS file | 1 // Copyright (c) 2013, the Dart project authors. Please see the AUTHORS file |
| 2 // for details. All rights reserved. Use of this source code is governed by a | 2 // for details. All rights reserved. Use of this source code is governed by a |
| 3 // BSD-style license that can be found in the LICENSE file. | 3 // BSD-style license that can be found in the LICENSE file. |
| 4 | 4 |
| 5 #include "vm/globals.h" // NOLINT | 5 #include "vm/globals.h" // NOLINT |
| 6 #if defined(TARGET_ARCH_X64) | 6 #if defined(TARGET_ARCH_X64) |
| 7 | 7 |
| 8 #include "vm/assembler.h" | 8 #include "vm/assembler.h" |
| 9 #include "vm/cpu.h" | 9 #include "vm/cpu.h" |
| 10 #include "vm/heap.h" | 10 #include "vm/heap.h" |
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| 778 | 778 |
| 779 void Assembler::orps(XmmRegister dst, XmmRegister src) { | 779 void Assembler::orps(XmmRegister dst, XmmRegister src) { |
| 780 AssemblerBuffer::EnsureCapacity ensured(&buffer_); | 780 AssemblerBuffer::EnsureCapacity ensured(&buffer_); |
| 781 EmitREX_RB(dst, src); | 781 EmitREX_RB(dst, src); |
| 782 EmitUint8(0x0F); | 782 EmitUint8(0x0F); |
| 783 EmitUint8(0x56); | 783 EmitUint8(0x56); |
| 784 EmitXmmRegisterOperand(dst & 7, src); | 784 EmitXmmRegisterOperand(dst & 7, src); |
| 785 } | 785 } |
| 786 | 786 |
| 787 void Assembler::notps(XmmRegister dst) { | 787 void Assembler::notps(XmmRegister dst) { |
| 788 static const struct ALIGN16 { | 788 // { 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF }; |
| 789 uint32_t a; | 789 movq(TMP, Address(THR, Thread::float_not_address_offset())); |
| 790 uint32_t b; | |
| 791 uint32_t c; | |
| 792 uint32_t d; | |
| 793 } float_not_constant = | |
| 794 { 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF }; | |
| 795 LoadImmediate( | |
| 796 TMP, Immediate(reinterpret_cast<intptr_t>(&float_not_constant))); | |
| 797 xorps(dst, Address(TMP, 0)); | 790 xorps(dst, Address(TMP, 0)); |
| 798 } | 791 } |
| 799 | 792 |
| 800 | 793 |
| 801 void Assembler::negateps(XmmRegister dst) { | 794 void Assembler::negateps(XmmRegister dst) { |
| 802 static const struct ALIGN16 { | 795 // { 0x80000000, 0x80000000, 0x80000000, 0x80000000 } |
| 803 uint32_t a; | 796 movq(TMP, Address(THR, Thread::float_negate_address_offset())); |
| 804 uint32_t b; | |
| 805 uint32_t c; | |
| 806 uint32_t d; | |
| 807 } float_negate_constant = | |
| 808 { 0x80000000, 0x80000000, 0x80000000, 0x80000000 }; | |
| 809 LoadImmediate( | |
| 810 TMP, Immediate(reinterpret_cast<intptr_t>(&float_negate_constant))); | |
| 811 xorps(dst, Address(TMP, 0)); | 797 xorps(dst, Address(TMP, 0)); |
| 812 } | 798 } |
| 813 | 799 |
| 814 | 800 |
| 815 void Assembler::absps(XmmRegister dst) { | 801 void Assembler::absps(XmmRegister dst) { |
| 816 static const struct ALIGN16 { | 802 // { 0x7FFFFFFF, 0x7FFFFFFF, 0x7FFFFFFF, 0x7FFFFFFF } |
| 817 uint32_t a; | 803 movq(TMP, Address(THR, Thread::float_absolute_address_offset())); |
| 818 uint32_t b; | |
| 819 uint32_t c; | |
| 820 uint32_t d; | |
| 821 } float_absolute_constant = | |
| 822 { 0x7FFFFFFF, 0x7FFFFFFF, 0x7FFFFFFF, 0x7FFFFFFF }; | |
| 823 LoadImmediate( | |
| 824 TMP, Immediate(reinterpret_cast<intptr_t>(&float_absolute_constant))); | |
| 825 andps(dst, Address(TMP, 0)); | 804 andps(dst, Address(TMP, 0)); |
| 826 } | 805 } |
| 827 | 806 |
| 828 | 807 |
| 829 void Assembler::zerowps(XmmRegister dst) { | 808 void Assembler::zerowps(XmmRegister dst) { |
| 830 static const struct ALIGN16 { | 809 // { 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0x00000000 } |
| 831 uint32_t a; | 810 movq(TMP, Address(THR, Thread::float_zerow_address_offset())); |
| 832 uint32_t b; | |
| 833 uint32_t c; | |
| 834 uint32_t d; | |
| 835 } float_zerow_constant = | |
| 836 { 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0x00000000 }; | |
| 837 LoadImmediate( | |
| 838 TMP, Immediate(reinterpret_cast<intptr_t>(&float_zerow_constant))); | |
| 839 andps(dst, Address(TMP, 0)); | 811 andps(dst, Address(TMP, 0)); |
| 840 } | 812 } |
| 841 | 813 |
| 842 | 814 |
| 843 void Assembler::cmppseq(XmmRegister dst, XmmRegister src) { | 815 void Assembler::cmppseq(XmmRegister dst, XmmRegister src) { |
| 844 AssemblerBuffer::EnsureCapacity ensured(&buffer_); | 816 AssemblerBuffer::EnsureCapacity ensured(&buffer_); |
| 845 EmitREX_RB(dst, src); | 817 EmitREX_RB(dst, src); |
| 846 EmitUint8(0x0F); | 818 EmitUint8(0x0F); |
| 847 EmitUint8(0xC2); | 819 EmitUint8(0xC2); |
| 848 EmitXmmRegisterOperand(dst & 7, src); | 820 EmitXmmRegisterOperand(dst & 7, src); |
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| 1010 ASSERT(dst <= XMM15); | 982 ASSERT(dst <= XMM15); |
| 1011 EmitUint8(0x66); | 983 EmitUint8(0x66); |
| 1012 EmitREX_RB(dst, src); | 984 EmitREX_RB(dst, src); |
| 1013 EmitUint8(0x0F); | 985 EmitUint8(0x0F); |
| 1014 EmitUint8(0x58); | 986 EmitUint8(0x58); |
| 1015 EmitXmmRegisterOperand(dst & 7, src); | 987 EmitXmmRegisterOperand(dst & 7, src); |
| 1016 } | 988 } |
| 1017 | 989 |
| 1018 | 990 |
| 1019 void Assembler::negatepd(XmmRegister dst) { | 991 void Assembler::negatepd(XmmRegister dst) { |
| 1020 static const struct ALIGN16 { | 992 // { 0x8000000000000000LL, 0x8000000000000000LL } |
| 1021 uint64_t a; | 993 movq(TMP, Address(THR, Thread::double_negate_address_offset())); |
| 1022 uint64_t b; | |
| 1023 } double_negate_constant = | |
| 1024 { 0x8000000000000000LL, 0x8000000000000000LL }; | |
| 1025 LoadImmediate( | |
| 1026 TMP, Immediate(reinterpret_cast<intptr_t>(&double_negate_constant))); | |
| 1027 xorpd(dst, Address(TMP, 0)); | 994 xorpd(dst, Address(TMP, 0)); |
| 1028 } | 995 } |
| 1029 | 996 |
| 1030 | 997 |
| 1031 void Assembler::subpd(XmmRegister dst, XmmRegister src) { | 998 void Assembler::subpd(XmmRegister dst, XmmRegister src) { |
| 1032 AssemblerBuffer::EnsureCapacity ensured(&buffer_); | 999 AssemblerBuffer::EnsureCapacity ensured(&buffer_); |
| 1033 ASSERT(src <= XMM15); | 1000 ASSERT(src <= XMM15); |
| 1034 ASSERT(dst <= XMM15); | 1001 ASSERT(dst <= XMM15); |
| 1035 EmitUint8(0x66); | 1002 EmitUint8(0x66); |
| 1036 EmitREX_RB(dst, src); | 1003 EmitREX_RB(dst, src); |
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| 1058 ASSERT(dst <= XMM15); | 1025 ASSERT(dst <= XMM15); |
| 1059 EmitUint8(0x66); | 1026 EmitUint8(0x66); |
| 1060 EmitREX_RB(dst, src); | 1027 EmitREX_RB(dst, src); |
| 1061 EmitUint8(0x0F); | 1028 EmitUint8(0x0F); |
| 1062 EmitUint8(0x5E); | 1029 EmitUint8(0x5E); |
| 1063 EmitXmmRegisterOperand(dst & 7, src); | 1030 EmitXmmRegisterOperand(dst & 7, src); |
| 1064 } | 1031 } |
| 1065 | 1032 |
| 1066 | 1033 |
| 1067 void Assembler::abspd(XmmRegister dst) { | 1034 void Assembler::abspd(XmmRegister dst) { |
| 1068 static const struct ALIGN16 { | 1035 // { 0x7FFFFFFFFFFFFFFFLL, 0x7FFFFFFFFFFFFFFFLL } |
| 1069 uint64_t a; | 1036 movq(TMP, Address(THR, Thread::double_abs_address_offset())); |
| 1070 uint64_t b; | |
| 1071 } double_absolute_const = | |
| 1072 { 0x7FFFFFFFFFFFFFFFLL, 0x7FFFFFFFFFFFFFFFLL }; | |
| 1073 LoadImmediate( | |
| 1074 TMP, Immediate(reinterpret_cast<intptr_t>(&double_absolute_const))); | |
| 1075 andpd(dst, Address(TMP, 0)); | 1037 andpd(dst, Address(TMP, 0)); |
| 1076 } | 1038 } |
| 1077 | 1039 |
| 1078 | 1040 |
| 1079 void Assembler::minpd(XmmRegister dst, XmmRegister src) { | 1041 void Assembler::minpd(XmmRegister dst, XmmRegister src) { |
| 1080 AssemblerBuffer::EnsureCapacity ensured(&buffer_); | 1042 AssemblerBuffer::EnsureCapacity ensured(&buffer_); |
| 1081 ASSERT(src <= XMM15); | 1043 ASSERT(src <= XMM15); |
| 1082 ASSERT(dst <= XMM15); | 1044 ASSERT(dst <= XMM15); |
| 1083 EmitUint8(0x66); | 1045 EmitUint8(0x66); |
| 1084 EmitREX_RB(dst, src); | 1046 EmitREX_RB(dst, src); |
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| 3153 Register temp = RCX; | 3115 Register temp = RCX; |
| 3154 pushq(temp); | 3116 pushq(temp); |
| 3155 leaq(temp, dest); | 3117 leaq(temp, dest); |
| 3156 addq(Address(temp, VerifiedMemory::offset()), inc_imm); | 3118 addq(Address(temp, VerifiedMemory::offset()), inc_imm); |
| 3157 popq(temp); | 3119 popq(temp); |
| 3158 } | 3120 } |
| 3159 } | 3121 } |
| 3160 | 3122 |
| 3161 | 3123 |
| 3162 void Assembler::DoubleNegate(XmmRegister d) { | 3124 void Assembler::DoubleNegate(XmmRegister d) { |
| 3163 static const struct ALIGN16 { | 3125 // {0x8000000000000000LL, 0x8000000000000000LL} |
| 3164 uint64_t a; | 3126 movq(TMP, Address(THR, Thread::double_negate_address_offset())); |
| 3165 uint64_t b; | |
| 3166 } double_negate_constant = | |
| 3167 {0x8000000000000000LL, 0x8000000000000000LL}; | |
| 3168 LoadImmediate( | |
| 3169 TMP, Immediate(reinterpret_cast<intptr_t>(&double_negate_constant))); | |
| 3170 xorpd(d, Address(TMP, 0)); | 3127 xorpd(d, Address(TMP, 0)); |
| 3171 } | 3128 } |
| 3172 | 3129 |
| 3173 | 3130 |
| 3174 void Assembler::DoubleAbs(XmmRegister reg) { | 3131 void Assembler::DoubleAbs(XmmRegister reg) { |
| 3175 static const struct ALIGN16 { | 3132 // {0x7FFFFFFFFFFFFFFFLL, 0x7FFFFFFFFFFFFFFFLL} |
| 3176 uint64_t a; | 3133 movq(TMP, Address(THR, Thread::double_abs_address_offset())); |
| 3177 uint64_t b; | |
| 3178 } double_abs_constant = | |
| 3179 {0x7FFFFFFFFFFFFFFFLL, 0x7FFFFFFFFFFFFFFFLL}; | |
| 3180 LoadImmediate(TMP, | |
| 3181 Immediate(reinterpret_cast<intptr_t>(&double_abs_constant))); | |
| 3182 andpd(reg, Address(TMP, 0)); | 3134 andpd(reg, Address(TMP, 0)); |
| 3183 } | 3135 } |
| 3184 | 3136 |
| 3185 | 3137 |
| 3186 void Assembler::Stop(const char* message, bool fixed_length_encoding) { | 3138 void Assembler::Stop(const char* message, bool fixed_length_encoding) { |
| 3187 int64_t message_address = reinterpret_cast<int64_t>(message); | 3139 int64_t message_address = reinterpret_cast<int64_t>(message); |
| 3188 if (FLAG_print_stop_message) { | 3140 if (FLAG_print_stop_message) { |
| 3189 pushq(TMP); // Preserve TMP register. | 3141 pushq(TMP); // Preserve TMP register. |
| 3190 pushq(RDI); // Preserve RDI register. | 3142 pushq(RDI); // Preserve RDI register. |
| 3191 if (fixed_length_encoding) { | 3143 if (fixed_length_encoding) { |
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| 3963 | 3915 |
| 3964 | 3916 |
| 3965 const char* Assembler::FpuRegisterName(FpuRegister reg) { | 3917 const char* Assembler::FpuRegisterName(FpuRegister reg) { |
| 3966 ASSERT((0 <= reg) && (reg < kNumberOfXmmRegisters)); | 3918 ASSERT((0 <= reg) && (reg < kNumberOfXmmRegisters)); |
| 3967 return xmm_reg_names[reg]; | 3919 return xmm_reg_names[reg]; |
| 3968 } | 3920 } |
| 3969 | 3921 |
| 3970 } // namespace dart | 3922 } // namespace dart |
| 3971 | 3923 |
| 3972 #endif // defined TARGET_ARCH_X64 | 3924 #endif // defined TARGET_ARCH_X64 |
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