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Issue 1497033002: Fuse icmp/fcmp with select (Closed) Base URL: https://chromium.googlesource.com/native_client/pnacl-subzero.git@master
Patch Set: Code review changes. Created 5 years ago
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1 //===- subzero/unittest/AssemblerX8632/XmmArith.cpp -----------------------===// 1 //===- subzero/unittest/AssemblerX8632/XmmArith.cpp -----------------------===//
2 // 2 //
3 // The Subzero Code Generator 3 // The Subzero Code Generator
4 // 4 //
5 // This file is distributed under the University of Illinois Open Source 5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details. 6 // License. See LICENSE.TXT for details.
7 // 7 //
8 //===----------------------------------------------------------------------===// 8 //===----------------------------------------------------------------------===//
9 #include "AssemblerX8632/TestUtil.h" 9 #include "AssemblerX8632/TestUtil.h"
10 10
(...skipping 372 matching lines...) Expand 10 before | Expand all | Expand 10 after
383 #undef TestPArith 383 #undef TestPArith
384 #undef TestPArithSize 384 #undef TestPArithSize
385 #undef TestPAndnXmmAddr 385 #undef TestPAndnXmmAddr
386 #undef TestPAndnXmmXmm 386 #undef TestPAndnXmmXmm
387 #undef TestPArithXmmImm 387 #undef TestPArithXmmImm
388 #undef TestPArithXmmAddr 388 #undef TestPArithXmmAddr
389 #undef TestPArithXmmXmm 389 #undef TestPArithXmmXmm
390 } 390 }
391 391
392 TEST_F(AssemblerX8632Test, ArithPS) { 392 TEST_F(AssemblerX8632Test, ArithPS) {
393 #define TestArithPSXmmXmm(Dst, Value0, Src, Value1, Inst, Op, Type) \ 393 #define TestArithPSXmmXmm(FloatSize, Dst, Value0, Src, Value1, Inst, Op, Type) \
394 do { \ 394 do { \
395 static constexpr char TestString[] = \ 395 static constexpr char TestString[] = \
396 "(" #Dst ", " #Value0 ", " #Src ", " #Value1 ", " #Inst ", " #Op \ 396 "(" #Dst ", " #Value0 ", " #Src ", " #Value1 ", " #Inst ", " #Op \
397 ", " #Type ")"; \ 397 ", " #Type ")"; \
398 const uint32_t T0 = allocateDqword(); \ 398 const uint32_t T0 = allocateDqword(); \
399 const Dqword V0 Value0; \ 399 const Dqword V0 Value0; \
400 const uint32_t T1 = allocateDqword(); \ 400 const uint32_t T1 = allocateDqword(); \
401 const Dqword V1 Value1; \ 401 const Dqword V1 Value1; \
402 \ 402 \
403 __ movups(XmmRegister::Encoded_Reg_##Dst, dwordAddress(T0)); \ 403 __ movups(XmmRegister::Encoded_Reg_##Dst, dwordAddress(T0)); \
404 __ movups(XmmRegister::Encoded_Reg_##Src, dwordAddress(T1)); \ 404 __ movups(XmmRegister::Encoded_Reg_##Src, dwordAddress(T1)); \
405 __ Inst(IceType_f32, XmmRegister::Encoded_Reg_##Dst, \ 405 __ Inst(IceType_f##FloatSize, XmmRegister::Encoded_Reg_##Dst, \
406 XmmRegister::Encoded_Reg_##Src); \ 406 XmmRegister::Encoded_Reg_##Src); \
407 \ 407 \
408 AssembledTest test = assemble(); \ 408 AssembledTest test = assemble(); \
409 test.setDqwordTo(T0, V0); \ 409 test.setDqwordTo(T0, V0); \
410 test.setDqwordTo(T1, V1); \ 410 test.setDqwordTo(T1, V1); \
411 test.run(); \ 411 test.run(); \
412 \ 412 \
413 ASSERT_EQ(packedAs<Type>(V0) Op V1, test.Dst<Dqword>()) << TestString; \ 413 ASSERT_EQ(packedAs<Type>(V0) Op V1, test.Dst<Dqword>()) << TestString; \
414 \ 414 \
415 reset(); \ 415 reset(); \
(...skipping 39 matching lines...) Expand 10 before | Expand all | Expand 10 after
455 AssembledTest test = assemble(); \ 455 AssembledTest test = assemble(); \
456 test.setDqwordTo(T0, V0); \ 456 test.setDqwordTo(T0, V0); \
457 test.setDqwordTo(T1, V1); \ 457 test.setDqwordTo(T1, V1); \
458 test.run(); \ 458 test.run(); \
459 \ 459 \
460 ASSERT_EQ(packedAs<Type>(V0) Op V1, test.Dst<Dqword>()) << TestString; \ 460 ASSERT_EQ(packedAs<Type>(V0) Op V1, test.Dst<Dqword>()) << TestString; \
461 \ 461 \
462 reset(); \ 462 reset(); \
463 } while (0) 463 } while (0)
464 464
465 #define TestMinMaxPS(Dst, Value0, Src, Value1, Inst, Type) \ 465 #define TestMinMaxPS(FloatSize, Dst, Value0, Src, Value1, Inst, Type) \
466 do { \ 466 do { \
467 static constexpr char TestString[] = \ 467 static constexpr char TestString[] = \
468 "(" #Dst ", " #Value0 ", " #Src ", " #Value1 ", " #Inst ", " #Type \ 468 "(" #Dst ", " #Value0 ", " #Src ", " #Value1 ", " #Inst ", " #Type \
469 ")"; \ 469 ")"; \
470 const uint32_t T0 = allocateDqword(); \ 470 const uint32_t T0 = allocateDqword(); \
471 const Dqword V0 Value0; \ 471 const Dqword V0 Value0; \
472 const uint32_t T1 = allocateDqword(); \ 472 const uint32_t T1 = allocateDqword(); \
473 const Dqword V1 Value1; \ 473 const Dqword V1 Value1; \
474 \ 474 \
475 __ movups(XmmRegister::Encoded_Reg_##Dst, dwordAddress(T0)); \ 475 __ movups(XmmRegister::Encoded_Reg_##Dst, dwordAddress(T0)); \
476 __ movups(XmmRegister::Encoded_Reg_##Src, dwordAddress(T1)); \ 476 __ movups(XmmRegister::Encoded_Reg_##Src, dwordAddress(T1)); \
477 __ Inst(XmmRegister::Encoded_Reg_##Dst, XmmRegister::Encoded_Reg_##Src); \ 477 __ Inst(IceType_f##FloatSize, XmmRegister::Encoded_Reg_##Dst, \
478 XmmRegister::Encoded_Reg_##Src); \
478 \ 479 \
479 AssembledTest test = assemble(); \ 480 AssembledTest test = assemble(); \
480 test.setDqwordTo(T0, V0); \ 481 test.setDqwordTo(T0, V0); \
481 test.setDqwordTo(T1, V1); \ 482 test.setDqwordTo(T1, V1); \
482 test.run(); \ 483 test.run(); \
483 \ 484 \
484 ASSERT_EQ(packedAs<Type>(V0).Inst(V1), test.Dst<Dqword>()) << TestString; \ 485 ASSERT_EQ(packedAs<Type>(V0).Inst(V1), test.Dst<Dqword>()) << TestString; \
485 \ 486 \
486 reset(); \ 487 reset(); \
487 } while (0) 488 } while (0)
488 489
489 #define TestArithPSXmmAddr(Dst, Value0, Value1, Inst, Op, Type) \ 490 #define TestArithPSXmmAddr(FloatSize, Dst, Value0, Value1, Inst, Op, Type) \
490 do { \ 491 do { \
491 static constexpr char TestString[] = \ 492 static constexpr char TestString[] = \
492 "(" #Dst ", " #Value0 ", Addr, " #Value1 ", " #Inst ", " #Op \ 493 "(" #Dst ", " #Value0 ", Addr, " #Value1 ", " #Inst ", " #Op \
493 ", " #Type ")"; \ 494 ", " #Type ")"; \
494 const uint32_t T0 = allocateDqword(); \ 495 const uint32_t T0 = allocateDqword(); \
495 const Dqword V0 Value0; \ 496 const Dqword V0 Value0; \
496 const uint32_t T1 = allocateDqword(); \ 497 const uint32_t T1 = allocateDqword(); \
497 const Dqword V1 Value1; \ 498 const Dqword V1 Value1; \
498 \ 499 \
499 __ movups(XmmRegister::Encoded_Reg_##Dst, dwordAddress(T0)); \ 500 __ movups(XmmRegister::Encoded_Reg_##Dst, dwordAddress(T0)); \
500 __ Inst(IceType_f32, XmmRegister::Encoded_Reg_##Dst, dwordAddress(T1)); \ 501 __ Inst(IceType_f##FloatSize, XmmRegister::Encoded_Reg_##Dst, \
502 dwordAddress(T1)); \
501 \ 503 \
502 AssembledTest test = assemble(); \ 504 AssembledTest test = assemble(); \
503 test.setDqwordTo(T0, V0); \ 505 test.setDqwordTo(T0, V0); \
504 test.setDqwordTo(T1, V1); \ 506 test.setDqwordTo(T1, V1); \
505 test.run(); \ 507 test.run(); \
506 \ 508 \
507 ASSERT_EQ(packedAs<Type>(V0) Op V1, test.Dst<Dqword>()) << TestString; \ 509 ASSERT_EQ(packedAs<Type>(V0) Op V1, test.Dst<Dqword>()) << TestString; \
508 \ 510 \
509 reset(); \ 511 reset(); \
510 } while (0) 512 } while (0)
511 513
512 #define TestArithPS(Dst, Src) \ 514 #define TestArithPS(Dst, Src) \
513 do { \ 515 do { \
514 TestArithPSXmmXmm(Dst, (1.0, 100.0, -1000.0, 20.0), Src, \ 516 TestArithPSXmmXmm(32, Dst, (1.0, 100.0, -1000.0, 20.0), Src, \
515 (0.55, 0.43, 0.23, 1.21), addps, +, float); \ 517 (0.55, 0.43, 0.23, 1.21), addps, +, float); \
516 TestArithPSXmmAddr(Dst, (1.0, 100.0, -1000.0, 20.0), \ 518 TestArithPSXmmAddr(32, Dst, (1.0, 100.0, -1000.0, 20.0), \
517 (0.55, 0.43, 0.23, 1.21), addps, +, float); \ 519 (0.55, 0.43, 0.23, 1.21), addps, +, float); \
518 TestArithPSXmmXmm(Dst, (1.0, 100.0, -1000.0, 20.0), Src, \ 520 TestArithPSXmmXmm(32, Dst, (1.0, 100.0, -1000.0, 20.0), Src, \
519 (0.55, 0.43, 0.23, 1.21), subps, -, float); \ 521 (0.55, 0.43, 0.23, 1.21), subps, -, float); \
520 TestArithPSXmmAddr(Dst, (1.0, 100.0, -1000.0, 20.0), \ 522 TestArithPSXmmAddr(32, Dst, (1.0, 100.0, -1000.0, 20.0), \
521 (0.55, 0.43, 0.23, 1.21), subps, -, float); \ 523 (0.55, 0.43, 0.23, 1.21), subps, -, float); \
522 TestArithPSXmmXmm(Dst, (1.0, 100.0, -1000.0, 20.0), Src, \ 524 TestArithPSXmmXmm(32, Dst, (1.0, 100.0, -1000.0, 20.0), Src, \
523 (0.55, 0.43, 0.23, 1.21), mulps, *, float); \ 525 (0.55, 0.43, 0.23, 1.21), mulps, *, float); \
524 TestArithPSXmmAddr(Dst, (1.0, 100.0, -1000.0, 20.0), \ 526 TestArithPSXmmAddr(32, Dst, (1.0, 100.0, -1000.0, 20.0), \
525 (0.55, 0.43, 0.23, 1.21), mulps, *, float); \ 527 (0.55, 0.43, 0.23, 1.21), mulps, *, float); \
526 TestArithPSXmmXmm(Dst, (1.0, 100.0, -1000.0, 20.0), Src, \ 528 TestArithPSXmmXmm(32, Dst, (1.0, 100.0, -1000.0, 20.0), Src, \
527 (0.55, 0.43, 0.23, 1.21), divps, /, float); \ 529 (0.55, 0.43, 0.23, 1.21), divps, /, float); \
528 TestArithPSXmmAddr(Dst, (1.0, 100.0, -1000.0, 20.0), \ 530 TestArithPSXmmAddr(32, Dst, (1.0, 100.0, -1000.0, 20.0), \
529 (0.55, 0.43, 0.23, 1.21), divps, /, float); \ 531 (0.55, 0.43, 0.23, 1.21), divps, /, float); \
530 TestArithPSXmmXmmUntyped(Dst, (1.0, 100.0, -1000.0, 20.0), Src, \ 532 TestArithPSXmmXmm(32, Dst, (1.0, 100.0, -1000.0, 20.0), Src, \
531 (0.55, 0.43, 0.23, 1.21), andps, &, float); \ 533 (0.55, 0.43, 0.23, 1.21), andps, &, float); \
532 TestArithPSXmmAddrUntyped(Dst, (1.0, 100.0, -1000.0, 20.0), \ 534 TestArithPSXmmAddr(32, Dst, (1.0, 100.0, -1000.0, 20.0), \
533 (0.55, 0.43, 0.23, 1.21), andps, &, float); \ 535 (0.55, 0.43, 0.23, 1.21), andps, &, float); \
534 TestArithPSXmmXmmUntyped(Dst, (1.0, -1000.0), Src, (0.55, 1.21), andpd, &, \ 536 TestArithPSXmmXmm(64, Dst, (1.0, -1000.0), Src, (0.55, 1.21), andps, &, \
535 double); \ 537 double); \
536 TestArithPSXmmAddrUntyped(Dst, (1.0, -1000.0), (0.55, 1.21), andpd, &, \ 538 TestArithPSXmmAddr(64, Dst, (1.0, -1000.0), (0.55, 1.21), andps, &, \
537 double); \ 539 double); \
538 TestArithPSXmmXmmUntyped(Dst, (1.0, 100.0, -1000.0, 20.0), Src, \ 540 TestArithPSXmmXmm(32, Dst, (1.0, 100.0, -1000.0, 20.0), Src, \
539 (0.55, 0.43, 0.23, 1.21), orps, |, float); \ 541 (0.55, 0.43, 0.23, 1.21), orps, |, float); \
540 TestArithPSXmmXmmUntyped(Dst, (1.0, -1000.0), Src, (0.55, 1.21), orpd, |, \ 542 TestArithPSXmmXmm(64, Dst, (1.0, -1000.0), Src, (0.55, 1.21), orps, |, \
541 double); \ 543 double); \
542 TestMinMaxPS(Dst, (1.0, 100.0, -1000.0, 20.0), Src, \ 544 TestMinMaxPS(32, Dst, (1.0, 100.0, -1000.0, 20.0), Src, \
543 (0.55, 0.43, 0.23, 1.21), minps, float); \ 545 (0.55, 0.43, 0.23, 1.21), minps, float); \
544 TestMinMaxPS(Dst, (1.0, 100.0, -1000.0, 20.0), Src, \ 546 TestMinMaxPS(32, Dst, (1.0, 100.0, -1000.0, 20.0), Src, \
545 (0.55, 0.43, 0.23, 1.21), maxps, float); \ 547 (0.55, 0.43, 0.23, 1.21), maxps, float); \
546 TestMinMaxPS(Dst, (1.0, -1000.0), Src, (0.55, 1.21), minpd, double); \ 548 TestMinMaxPS(64, Dst, (1.0, -1000.0), Src, (0.55, 1.21), minps, double); \
547 TestMinMaxPS(Dst, (1.0, -1000.0), Src, (0.55, 1.21), maxpd, double); \ 549 TestMinMaxPS(64, Dst, (1.0, -1000.0), Src, (0.55, 1.21), maxps, double); \
548 TestArithPSXmmXmmUntyped(Dst, (1.0, 100.0, -1000.0, 20.0), Src, \ 550 TestArithPSXmmXmm(32, Dst, (1.0, 100.0, -1000.0, 20.0), Src, \
549 (0.55, 0.43, 0.23, 1.21), xorps, ^, float); \ 551 (0.55, 0.43, 0.23, 1.21), xorps, ^, float); \
550 TestArithPSXmmAddrUntyped(Dst, (1.0, 100.0, -1000.0, 20.0), \ 552 TestArithPSXmmAddr(32, Dst, (1.0, 100.0, -1000.0, 20.0), \
551 (0.55, 0.43, 0.23, 1.21), xorps, ^, float); \ 553 (0.55, 0.43, 0.23, 1.21), xorps, ^, float); \
552 TestArithPSXmmXmmUntyped(Dst, (1.0, -1000.0), Src, (0.55, 1.21), xorpd, ^, \ 554 TestArithPSXmmXmm(64, Dst, (1.0, -1000.0), Src, (0.55, 1.21), xorps, ^, \
553 double); \ 555 double); \
554 TestArithPSXmmAddrUntyped(Dst, (1.0, -1000.0), (0.55, 1.21), xorpd, ^, \ 556 TestArithPSXmmAddr(64, Dst, (1.0, -1000.0), (0.55, 1.21), xorps, ^, \
555 double); \ 557 double); \
556 } while (0) 558 } while (0)
557 559
558 #if 0 560 #if 0
559 561
560 #endif 562 #endif
561 563
562 TestArithPS(xmm0, xmm1); 564 TestArithPS(xmm0, xmm1);
563 TestArithPS(xmm1, xmm2); 565 TestArithPS(xmm1, xmm2);
564 TestArithPS(xmm2, xmm3); 566 TestArithPS(xmm2, xmm3);
565 TestArithPS(xmm3, xmm4); 567 TestArithPS(xmm3, xmm4);
(...skipping 102 matching lines...) Expand 10 before | Expand all | Expand 10 after
668 TestBlending(xmm5, xmm6); 670 TestBlending(xmm5, xmm6);
669 TestBlending(xmm6, xmm7); 671 TestBlending(xmm6, xmm7);
670 TestBlending(xmm7, xmm1); 672 TestBlending(xmm7, xmm1);
671 673
672 #undef TestBlending 674 #undef TestBlending
673 #undef TestBlendingXmmAddr 675 #undef TestBlendingXmmAddr
674 #undef TestBlendingXmmXmm 676 #undef TestBlendingXmmXmm
675 } 677 }
676 678
677 TEST_F(AssemblerX8632Test, Cmpps) { 679 TEST_F(AssemblerX8632Test, Cmpps) {
678 #define TestCmppsXmmXmm(Dst, Src, C, Op) \ 680 #define TestCmppsXmmXmm(FloatSize, Dst, Value0, Src, Value1, C, Op, Type) \
679 do { \ 681 do { \
680 static constexpr char TestString[] = \ 682 static constexpr char TestString[] = \
681 "(" #Src ", " #Dst ", " #C ", " #Op ")"; \ 683 "(" #Src ", " #Dst ", " #C ", " #Op ")"; \
682 const uint32_t T0 = allocateDqword(); \ 684 const uint32_t T0 = allocateDqword(); \
683 const Dqword V0(-1.0, 1.0, 3.14, 1024.5); \ 685 const Dqword V0 Value0; \
684 const uint32_t T1 = allocateDqword(); \ 686 const uint32_t T1 = allocateDqword(); \
685 const Dqword V1(-1.0, 1.0, 3.14, 1024.5); \ 687 const Dqword V1 Value1; \
686 \ 688 \
687 __ movups(XmmRegister::Encoded_Reg_##Dst, dwordAddress(T0)); \ 689 __ movups(XmmRegister::Encoded_Reg_##Dst, dwordAddress(T0)); \
688 __ movups(XmmRegister::Encoded_Reg_##Src, dwordAddress(T1)); \ 690 __ movups(XmmRegister::Encoded_Reg_##Src, dwordAddress(T1)); \
689 __ cmpps(XmmRegister::Encoded_Reg_##Dst, XmmRegister::Encoded_Reg_##Src, \ 691 __ cmpps(IceType_f##FloatSize, XmmRegister::Encoded_Reg_##Dst, \
690 Cond::Cmpps_##C); \ 692 XmmRegister::Encoded_Reg_##Src, Cond::Cmpps_##C); \
691 \ 693 \
692 AssembledTest test = assemble(); \ 694 AssembledTest test = assemble(); \
693 test.setDqwordTo(T0, V0); \ 695 test.setDqwordTo(T0, V0); \
694 test.setDqwordTo(T1, V1); \ 696 test.setDqwordTo(T1, V1); \
695 test.run(); \ 697 test.run(); \
696 \ 698 \
697 ASSERT_EQ(packedAs<float>(V0) Op V1, test.Dst<Dqword>()) << TestString; \ 699 ASSERT_EQ(packedAs<Type>(V0) Op V1, test.Dst<Dqword>()) << TestString; \
698 ; \ 700 ; \
699 reset(); \ 701 reset(); \
700 } while (0) 702 } while (0)
701 703
702 #define TestCmppsXmmAddr(Dst, C, Op) \ 704 #define TestCmppsXmmAddr(FloatSize, Dst, Value0, Value1, C, Op, Type) \
703 do { \ 705 do { \
704 static constexpr char TestString[] = "(" #Dst ", Addr, " #C ", " #Op ")"; \ 706 static constexpr char TestString[] = "(" #Dst ", Addr, " #C ", " #Op ")"; \
705 const uint32_t T0 = allocateDqword(); \ 707 const uint32_t T0 = allocateDqword(); \
706 const Dqword V0(-1.0, 1.0, 3.14, 1024.5); \ 708 const Dqword V0 Value0; \
707 const uint32_t T1 = allocateDqword(); \ 709 const uint32_t T1 = allocateDqword(); \
708 const Dqword V1(-1.0, 1.0, 3.14, 1024.5); \ 710 const Dqword V1 Value1; \
709 \ 711 \
710 __ movups(XmmRegister::Encoded_Reg_##Dst, dwordAddress(T0)); \ 712 __ movups(XmmRegister::Encoded_Reg_##Dst, dwordAddress(T0)); \
711 __ cmpps(XmmRegister::Encoded_Reg_##Dst, dwordAddress(T1), \ 713 __ cmpps(IceType_f##FloatSize, XmmRegister::Encoded_Reg_##Dst, \
712 Cond::Cmpps_##C); \ 714 dwordAddress(T1), Cond::Cmpps_##C); \
713 \ 715 \
714 AssembledTest test = assemble(); \ 716 AssembledTest test = assemble(); \
715 test.setDqwordTo(T0, V0); \ 717 test.setDqwordTo(T0, V0); \
716 test.setDqwordTo(T1, V1); \ 718 test.setDqwordTo(T1, V1); \
717 test.run(); \ 719 test.run(); \
718 \ 720 \
719 ASSERT_EQ(packedAs<float>(V0) Op V1, test.Dst<Dqword>()) << TestString; \ 721 ASSERT_EQ(packedAs<Type>(V0) Op V1, test.Dst<Dqword>()) << TestString; \
720 ; \ 722 ; \
721 reset(); \ 723 reset(); \
722 } while (0) 724 } while (0)
723 725
724 #define TestCmppsOrdUnordXmmXmm(Dst, Src, C) \ 726 #define TestCmppsOrdUnordXmmXmm(FloatSize, Dst, Value0, Src, Value1, C, Type) \
725 do { \ 727 do { \
726 static constexpr char TestString[] = "(" #Src ", " #Dst ", " #C ")"; \ 728 static constexpr char TestString[] = "(" #Src ", " #Dst ", " #C ")"; \
727 const uint32_t T0 = allocateDqword(); \ 729 const uint32_t T0 = allocateDqword(); \
728 const Dqword V0(1.0, 1.0, std::numeric_limits<float>::quiet_NaN(), \ 730 const Dqword V0(1.0, 1.0, std::numeric_limits<float>::quiet_NaN(), \
729 std::numeric_limits<float>::quiet_NaN()); \ 731 std::numeric_limits<float>::quiet_NaN()); \
730 const uint32_t T1 = allocateDqword(); \ 732 const uint32_t T1 = allocateDqword(); \
731 const Dqword V1(1.0, std::numeric_limits<float>::quiet_NaN(), 1.0, \ 733 const Dqword V1(1.0, std::numeric_limits<float>::quiet_NaN(), 1.0, \
732 std::numeric_limits<float>::quiet_NaN()); \ 734 std::numeric_limits<float>::quiet_NaN()); \
733 \ 735 \
734 __ movups(XmmRegister::Encoded_Reg_##Dst, dwordAddress(T0)); \ 736 __ movups(XmmRegister::Encoded_Reg_##Dst, dwordAddress(T0)); \
735 __ movups(XmmRegister::Encoded_Reg_##Src, dwordAddress(T1)); \ 737 __ movups(XmmRegister::Encoded_Reg_##Src, dwordAddress(T1)); \
736 __ cmpps(XmmRegister::Encoded_Reg_##Dst, XmmRegister::Encoded_Reg_##Src, \ 738 __ cmpps(IceType_f##FloatSize, XmmRegister::Encoded_Reg_##Dst, \
737 Cond::Cmpps_##C); \ 739 XmmRegister::Encoded_Reg_##Src, Cond::Cmpps_##C); \
738 \ 740 \
739 AssembledTest test = assemble(); \ 741 AssembledTest test = assemble(); \
740 test.setDqwordTo(T0, V0); \ 742 test.setDqwordTo(T0, V0); \
741 test.setDqwordTo(T1, V1); \ 743 test.setDqwordTo(T1, V1); \
742 test.run(); \ 744 test.run(); \
743 \ 745 \
744 ASSERT_EQ(packedAs<float>(V0).C(V1), test.Dst<Dqword>()) << TestString; \ 746 ASSERT_EQ(packedAs<Type>(V0).C(V1), test.Dst<Dqword>()) << TestString; \
745 ; \ 747 ; \
746 reset(); \ 748 reset(); \
747 } while (0) 749 } while (0)
748 750
749 #define TestCmppsOrdUnordXmmAddr(Dst, C) \ 751 #define TestCmppsOrdUnordXmmAddr(FloatSize, Dst, Value0, Value1, C, Type) \
750 do { \ 752 do { \
751 static constexpr char TestString[] = "(" #Dst ", " #C ")"; \ 753 static constexpr char TestString[] = "(" #Dst ", " #C ")"; \
752 const uint32_t T0 = allocateDqword(); \ 754 const uint32_t T0 = allocateDqword(); \
753 const Dqword V0(1.0, 1.0, std::numeric_limits<float>::quiet_NaN(), \ 755 const Dqword V0(1.0, 1.0, std::numeric_limits<float>::quiet_NaN(), \
754 std::numeric_limits<float>::quiet_NaN()); \ 756 std::numeric_limits<float>::quiet_NaN()); \
755 const uint32_t T1 = allocateDqword(); \ 757 const uint32_t T1 = allocateDqword(); \
756 const Dqword V1(1.0, std::numeric_limits<float>::quiet_NaN(), 1.0, \ 758 const Dqword V1(1.0, std::numeric_limits<float>::quiet_NaN(), 1.0, \
757 std::numeric_limits<float>::quiet_NaN()); \ 759 std::numeric_limits<float>::quiet_NaN()); \
758 \ 760 \
759 __ movups(XmmRegister::Encoded_Reg_##Dst, dwordAddress(T0)); \ 761 __ movups(XmmRegister::Encoded_Reg_##Dst, dwordAddress(T0)); \
760 __ cmpps(XmmRegister::Encoded_Reg_##Dst, dwordAddress(T1), \ 762 __ cmpps(IceType_f##FloatSize, XmmRegister::Encoded_Reg_##Dst, \
761 Cond::Cmpps_##C); \ 763 dwordAddress(T1), Cond::Cmpps_##C); \
762 \ 764 \
763 AssembledTest test = assemble(); \ 765 AssembledTest test = assemble(); \
764 test.setDqwordTo(T0, V0); \ 766 test.setDqwordTo(T0, V0); \
765 test.setDqwordTo(T1, V1); \ 767 test.setDqwordTo(T1, V1); \
766 test.run(); \ 768 test.run(); \
767 \ 769 \
768 ASSERT_EQ(packedAs<float>(V0).C(V1), test.Dst<Dqword>()) << TestString; \ 770 ASSERT_EQ(packedAs<Type>(V0).C(V1), test.Dst<Dqword>()) << TestString; \
769 ; \ 771 ; \
770 reset(); \ 772 reset(); \
771 } while (0) 773 } while (0)
772 774
773 #define TestCmpps(Dst, Src) \ 775 #define TestCmpps(FloatSize, Dst, Value0, Src, Value1, Type) \
774 do { \ 776 do { \
775 TestCmppsXmmXmm(Dst, Src, eq, == ); \ 777 TestCmppsXmmXmm(FloatSize, Dst, Value0, Src, Value1, eq, ==, Type); \
776 TestCmppsXmmAddr(Dst, eq, == ); \ 778 TestCmppsXmmAddr(FloatSize, Dst, Value0, Value1, eq, ==, Type); \
777 TestCmppsXmmXmm(Dst, Src, eq, == ); \ 779 TestCmppsXmmXmm(FloatSize, Dst, Value0, Src, Value1, eq, ==, Type); \
778 TestCmppsXmmAddr(Dst, eq, == ); \ 780 TestCmppsXmmAddr(FloatSize, Dst, Value0, Value1, eq, ==, Type); \
779 TestCmppsXmmXmm(Dst, Src, eq, == ); \ 781 TestCmppsXmmXmm(FloatSize, Dst, Value0, Src, Value1, eq, ==, Type); \
780 TestCmppsXmmAddr(Dst, eq, == ); \ 782 TestCmppsXmmAddr(FloatSize, Dst, Value0, Value1, eq, ==, Type); \
781 TestCmppsOrdUnordXmmXmm(Dst, Src, unord); \ 783 TestCmppsOrdUnordXmmXmm(FloatSize, Dst, Value0, Src, Value1, unord, Type); \
782 TestCmppsOrdUnordXmmAddr(Dst, unord); \ 784 TestCmppsOrdUnordXmmAddr(FloatSize, Dst, Value0, Value1, unord, Type); \
783 TestCmppsXmmXmm(Dst, Src, eq, == ); \ 785 TestCmppsXmmXmm(FloatSize, Dst, Value0, Src, Value1, eq, ==, Type); \
784 TestCmppsXmmAddr(Dst, eq, == ); \ 786 TestCmppsXmmAddr(FloatSize, Dst, Value0, Value1, eq, ==, Type); \
785 TestCmppsXmmXmm(Dst, Src, eq, == ); \ 787 TestCmppsXmmXmm(FloatSize, Dst, Value0, Src, Value1, eq, ==, Type); \
786 TestCmppsXmmAddr(Dst, eq, == ); \ 788 TestCmppsXmmAddr(FloatSize, Dst, Value0, Value1, eq, ==, Type); \
787 TestCmppsXmmXmm(Dst, Src, eq, == ); \ 789 TestCmppsXmmXmm(FloatSize, Dst, Value0, Src, Value1, eq, ==, Type); \
788 TestCmppsXmmAddr(Dst, eq, == ); \ 790 TestCmppsXmmAddr(FloatSize, Dst, Value0, Value1, eq, ==, Type); \
789 TestCmppsOrdUnordXmmXmm(Dst, Src, unord); \ 791 if (FloatSize == 32) { \
790 TestCmppsOrdUnordXmmAddr(Dst, unord); \ 792 TestCmppsOrdUnordXmmXmm( \
793 32, Dst, (1.0, 1.0, std::numeric_limits<float>::quiet_NaN(), \
794 std::numeric_limits<float>::quiet_NaN()), \
795 Src, (1.0, std::numeric_limits<float>::quiet_NaN(), 1.0, \
796 std::numeric_limits<float>::quiet_NaN()), \
797 unord, Type); \
798 TestCmppsOrdUnordXmmAddr( \
799 32, Dst, (1.0, 1.0, std::numeric_limits<float>::quiet_NaN(), \
800 std::numeric_limits<float>::quiet_NaN()), \
801 (1.0, std::numeric_limits<float>::quiet_NaN(), 1.0, \
802 std::numeric_limits<float>::quiet_NaN()), \
803 unord, Type); \
804 } else { \
805 TestCmppsOrdUnordXmmXmm(64, Dst, \
806 (1.0, std::numeric_limits<double>::quiet_NaN()), \
807 Src, (std::numeric_limits<double>::quiet_NaN(), \
808 std::numeric_limits<double>::quiet_NaN()), \
809 unord, Type); \
810 TestCmppsOrdUnordXmmXmm(64, Dst, (1.0, 1.0), Src, \
811 (1.0, std::numeric_limits<double>::quiet_NaN()), \
812 unord, Type); \
813 TestCmppsOrdUnordXmmAddr( \
814 64, Dst, (1.0, std::numeric_limits<double>::quiet_NaN()), \
815 (std::numeric_limits<double>::quiet_NaN(), \
816 std::numeric_limits<double>::quiet_NaN()), \
817 unord, Type); \
818 TestCmppsOrdUnordXmmAddr( \
819 64, Dst, (1.0, 1.0), \
820 (1.0, std::numeric_limits<double>::quiet_NaN()), unord, Type); \
821 } \
791 } while (0) 822 } while (0)
792 823
793 TestCmpps(xmm0, xmm1); 824 #define TestCmppsSize(FloatSize, Value0, Value1, Type) \
794 TestCmpps(xmm1, xmm2); 825 do { \
795 TestCmpps(xmm2, xmm3); 826 TestCmpps(FloatSize, xmm0, Value0, xmm1, Value1, Type); \
796 TestCmpps(xmm3, xmm4); 827 TestCmpps(FloatSize, xmm1, Value0, xmm2, Value1, Type); \
797 TestCmpps(xmm4, xmm5); 828 TestCmpps(FloatSize, xmm2, Value0, xmm3, Value1, Type); \
798 TestCmpps(xmm5, xmm6); 829 TestCmpps(FloatSize, xmm3, Value0, xmm4, Value1, Type); \
799 TestCmpps(xmm6, xmm7); 830 TestCmpps(FloatSize, xmm4, Value0, xmm5, Value1, Type); \
800 TestCmpps(xmm7, xmm0); 831 TestCmpps(FloatSize, xmm5, Value0, xmm6, Value1, Type); \
832 TestCmpps(FloatSize, xmm6, Value0, xmm7, Value1, Type); \
833 TestCmpps(FloatSize, xmm7, Value0, xmm0, Value1, Type); \
834 } while (0)
835
836 TestCmppsSize(32, (-1.0, 1.0, 3.14, 1024.5), (-1.0, 1.0, 3.14, 1024.5),
837 float);
838 TestCmppsSize(64, (1.0, -1000.0), (0.55, 1.21), double);
801 839
802 #undef TestCmpps 840 #undef TestCmpps
803 #undef TestCmppsOrdUnordXmmAddr 841 #undef TestCmppsOrdUnordXmmAddr
804 #undef TestCmppsOrdUnordXmmXmm 842 #undef TestCmppsOrdUnordXmmXmm
805 #undef TestCmppsXmmAddr 843 #undef TestCmppsXmmAddr
806 #undef TestCmppsXmmXmm 844 #undef TestCmppsXmmXmm
807 } 845 }
808 846
809 TEST_F(AssemblerX8632Test, Sqrtps_Rsqrtps_Reciprocalps_Sqrtpd) { 847 TEST_F(AssemblerX8632Test, Sqrtps_Rsqrtps_Reciprocalps_Sqrtpd) {
810 #define TestImplSingle(Dst, Inst, Expect) \ 848 #define TestImplSingle(Dst, Inst, Expect) \
(...skipping 996 matching lines...) Expand 10 before | Expand all | Expand 10 after
1807 TestImpl(xmm6, ebx, 7); 1845 TestImpl(xmm6, ebx, 7);
1808 TestImpl(xmm7, ecx, 8); 1846 TestImpl(xmm7, ecx, 8);
1809 1847
1810 #undef TestImpl 1848 #undef TestImpl
1811 } 1849 }
1812 1850
1813 } // end of anonymous namespace 1851 } // end of anonymous namespace
1814 } // end of namespace Test 1852 } // end of namespace Test
1815 } // end of namespace X8632 1853 } // end of namespace X8632
1816 } // end of namespace Ice 1854 } // end of namespace Ice
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