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Issue 1497033002: Fuse icmp/fcmp with select (Closed) Base URL: https://chromium.googlesource.com/native_client/pnacl-subzero.git@master
Patch Set: Code review changes. Created 5 years ago
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1 ; This tries to be a comprehensive test of i64 operations, in 1 ; This tries to be a comprehensive test of i64 operations, in
2 ; particular the patterns for lowering i64 operations into constituent 2 ; particular the patterns for lowering i64 operations into constituent
3 ; i32 operations on x86-32. 3 ; i32 operations on x86-32.
4 4
5 ; RUN: %if --need=target_X8632 --command %p2i --filetype=obj --disassemble \ 5 ; RUN: %if --need=target_X8632 --command %p2i --filetype=obj --disassemble \
6 ; RUN: --target x8632 -i %s --args -O2 -allow-externally-defined-symbols \ 6 ; RUN: --target x8632 -i %s --args -O2 -allow-externally-defined-symbols \
7 ; RUN: | %if --need=target_X8632 --command FileCheck %s 7 ; RUN: | %if --need=target_X8632 --command FileCheck %s
8 8
9 ; RUN: %if --need=target_X8632 --command %p2i --filetype=obj --disassemble \ 9 ; RUN: %if --need=target_X8632 --command %p2i --filetype=obj --disassemble \
10 ; RUN: --target x8632 -i %s --args -Om1 -allow-externally-defined-symbols \ 10 ; RUN: --target x8632 -i %s --args -Om1 -allow-externally-defined-symbols \
(...skipping 1632 matching lines...) Expand 10 before | Expand all | Expand 10 after
1643 ; ARM32: str [[REG1]], [r[[REG:.*]], #4] 1643 ; ARM32: str [[REG1]], [r[[REG:.*]], #4]
1644 ; ARM32: str [[REG2]], [r[[REG]]] 1644 ; ARM32: str [[REG2]], [r[[REG]]]
1645 1645
1646 define internal i64 @select64VarVar(i64 %a, i64 %b) { 1646 define internal i64 @select64VarVar(i64 %a, i64 %b) {
1647 entry: 1647 entry:
1648 %cmp = icmp ult i64 %a, %b 1648 %cmp = icmp ult i64 %a, %b
1649 %cond = select i1 %cmp, i64 %a, i64 %b 1649 %cond = select i1 %cmp, i64 %a, i64 %b
1650 ret i64 %cond 1650 ret i64 %cond
1651 } 1651 }
1652 ; CHECK-LABEL: select64VarVar 1652 ; CHECK-LABEL: select64VarVar
1653 ; CHECK: mov
1654 ; CHECK: mov
1653 ; CHECK: cmp 1655 ; CHECK: cmp
1654 ; CHECK: jb 1656 ; CHECK: jb
1655 ; CHECK: ja 1657 ; CHECK: ja
1656 ; CHECK: cmp 1658 ; CHECK: cmp
1657 ; CHECK: jb 1659 ; CHECK: jb
1658 ; CHECK: cmp 1660 ; CHECK: mov
1659 ; CHECK: cmovne 1661 ; CHECK: mov
1660 ; 1662 ;
1661 ; OPTM1-LABEL: select64VarVar 1663 ; OPTM1-LABEL: select64VarVar
1662 ; OPTM1: cmp 1664 ; OPTM1: cmp
1663 ; OPTM1: jb 1665 ; OPTM1: jb
1664 ; OPTM1: ja 1666 ; OPTM1: ja
1665 ; OPTM1: cmp 1667 ; OPTM1: cmp
1666 ; OPTM1: jb 1668 ; OPTM1: jb
1667 ; OPTM1: cmp 1669 ; OPTM1: cmp
1668 ; OPTM1: cmovne 1670 ; OPTM1: cmovne
1669 1671
1670 ; ARM32-LABEL: select64VarVar 1672 ; ARM32-LABEL: select64VarVar
1671 ; ARM32: cmp 1673 ; ARM32: cmp
1672 ; ARM32: cmpeq 1674 ; ARM32: cmpeq
1673 ; ARM32-OM1: tst 1675 ; ARM32-OM1: tst
1674 ; ARM32-OM1: movne 1676 ; ARM32-OM1: movne
1675 ; ARM32-O2: movcc 1677 ; ARM32-O2: movcc
1676 ; ARM32-OM1: movne 1678 ; ARM32-OM1: movne
1677 ; ARM32-O2: movcc 1679 ; ARM32-O2: movcc
1678 1680
1679 define internal i64 @select64VarConst(i64 %a, i64 %b) { 1681 define internal i64 @select64VarConst(i64 %a, i64 %b) {
1680 entry: 1682 entry:
1681 %cmp = icmp ult i64 %a, %b 1683 %cmp = icmp ult i64 %a, %b
1682 %cond = select i1 %cmp, i64 %a, i64 -2401053092306725256 1684 %cond = select i1 %cmp, i64 %a, i64 -2401053092306725256
1683 ret i64 %cond 1685 ret i64 %cond
1684 } 1686 }
1685 ; CHECK-LABEL: select64VarConst 1687 ; CHECK-LABEL: select64VarConst
1688 ; CHECK: mov
1689 ; CHECK: mov
1686 ; CHECK: cmp 1690 ; CHECK: cmp
1687 ; CHECK: jb 1691 ; CHECK: jb
1688 ; CHECK: ja 1692 ; CHECK: ja
1689 ; CHECK: cmp 1693 ; CHECK: cmp
1690 ; CHECK: jb 1694 ; CHECK: jb
1691 ; CHECK: cmp 1695 ; CHECK: mov
1692 ; CHECK: cmovne 1696 ; CHECK: mov
1693 ; 1697 ;
1694 ; OPTM1-LABEL: select64VarConst 1698 ; OPTM1-LABEL: select64VarConst
1695 ; OPTM1: cmp 1699 ; OPTM1: cmp
1696 ; OPTM1: jb 1700 ; OPTM1: jb
1697 ; OPTM1: ja 1701 ; OPTM1: ja
1698 ; OPTM1: cmp 1702 ; OPTM1: cmp
1699 ; OPTM1: jb 1703 ; OPTM1: jb
1700 ; OPTM1: cmp 1704 ; OPTM1: cmp
1701 ; OPTM1: cmovne 1705 ; OPTM1: cmovne
1702 1706
(...skipping 10 matching lines...) Expand all
1713 ; ARM32-O2: mov 1717 ; ARM32-O2: mov
1714 ; ARM32-O2: mov 1718 ; ARM32-O2: mov
1715 1719
1716 define internal i64 @select64ConstVar(i64 %a, i64 %b) { 1720 define internal i64 @select64ConstVar(i64 %a, i64 %b) {
1717 entry: 1721 entry:
1718 %cmp = icmp ult i64 %a, %b 1722 %cmp = icmp ult i64 %a, %b
1719 %cond = select i1 %cmp, i64 -2401053092306725256, i64 %b 1723 %cond = select i1 %cmp, i64 -2401053092306725256, i64 %b
1720 ret i64 %cond 1724 ret i64 %cond
1721 } 1725 }
1722 ; CHECK-LABEL: select64ConstVar 1726 ; CHECK-LABEL: select64ConstVar
1727 ; CHECK: mov
1728 ; CHECK: mov
1723 ; CHECK: cmp 1729 ; CHECK: cmp
1724 ; CHECK: jb 1730 ; CHECK: jb
1725 ; CHECK: ja 1731 ; CHECK: ja
1726 ; CHECK: cmp 1732 ; CHECK: cmp
1727 ; CHECK: jb 1733 ; CHECK: jb
1728 ; CHECK: cmp 1734 ; CHECK: mov
1729 ; CHECK: cmove 1735 ; CHECK: mov
1730 ; 1736 ;
1731 ; OPTM1-LABEL: select64ConstVar 1737 ; OPTM1-LABEL: select64ConstVar
1732 ; OPTM1: cmp 1738 ; OPTM1: cmp
1733 ; OPTM1: jb 1739 ; OPTM1: jb
1734 ; OPTM1: ja 1740 ; OPTM1: ja
1735 ; OPTM1: cmp 1741 ; OPTM1: cmp
1736 ; OPTM1: jb 1742 ; OPTM1: jb
1737 ; OPTM1: cmp 1743 ; OPTM1: cmp
1738 ; OPTM1: cmove 1744 ; OPTM1: cmove
1739 1745
(...skipping 106 matching lines...) Expand 10 before | Expand all | Expand 10 after
1846 ; CHECK-LABEL: phi64Undef 1852 ; CHECK-LABEL: phi64Undef
1847 ; CHECK: mov {{.*}},0x0 1853 ; CHECK: mov {{.*}},0x0
1848 ; CHECK: mov {{.*}},0x0 1854 ; CHECK: mov {{.*}},0x0
1849 ; OPTM1-LABEL: phi64Undef 1855 ; OPTM1-LABEL: phi64Undef
1850 ; OPTM1: mov {{.*}},0x0 1856 ; OPTM1: mov {{.*}},0x0
1851 ; OPTM1: mov {{.*}},0x0 1857 ; OPTM1: mov {{.*}},0x0
1852 ; ARM32-LABEL: phi64Undef 1858 ; ARM32-LABEL: phi64Undef
1853 ; ARM32: mov {{.*}} #0 1859 ; ARM32: mov {{.*}} #0
1854 ; ARM32: mov {{.*}} #0 1860 ; ARM32: mov {{.*}} #0
1855 1861
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