Chromium Code Reviews
chromiumcodereview-hr@appspot.gserviceaccount.com (chromiumcodereview-hr) | Please choose your nickname with Settings | Help | Chromium Project | Gerrit Changes | Sign out
(153)

Side by Side Diff: src/IceAssemblerARM32.h

Issue 1494433005: Add RSB instruction to the ARM integrated assembler. (Closed) Base URL: https://chromium.googlesource.com/native_client/pnacl-subzero.git@master
Patch Set: Reformat and update Dart assembler files. Created 5 years ago
Use n/p to move between diff chunks; N/P to move between comments. Draft comments are only viewable by you.
Jump to:
View unified diff | Download patch
« no previous file with comments | « src/DartARM32/assembler_arm.cc ('k') | src/IceAssemblerARM32.cpp » ('j') | no next file with comments »
Toggle Intra-line Diffs ('i') | Expand Comments ('e') | Collapse Comments ('c') | Show Comments Hide Comments ('s')
OLDNEW
1 //===- subzero/src/IceAssemblerARM32.h - Assembler for ARM32 ----*- C++ -*-===// 1 //===- subzero/src/IceAssemblerARM32.h - Assembler for ARM32 ----*- C++ -*-===//
2 // 2 //
3 // Copyright (c) 2013, the Dart project authors. Please see the AUTHORS file 3 // Copyright (c) 2013, the Dart project authors. Please see the AUTHORS file
4 // for details. All rights reserved. Use of this source code is governed by a 4 // for details. All rights reserved. Use of this source code is governed by a
5 // BSD-style license that can be found in the LICENSE file. 5 // BSD-style license that can be found in the LICENSE file.
6 // 6 //
7 // Modified by the Subzero authors. 7 // Modified by the Subzero authors.
8 // 8 //
9 //===----------------------------------------------------------------------===// 9 //===----------------------------------------------------------------------===//
10 // 10 //
(...skipping 231 matching lines...) Expand 10 before | Expand all | Expand 10 after
242 void pop(const Operand *OpRt, CondARM32::Cond Cond); 242 void pop(const Operand *OpRt, CondARM32::Cond Cond);
243 243
244 // Note: Registers is a bitset, where bit n corresponds to register Rn. 244 // Note: Registers is a bitset, where bit n corresponds to register Rn.
245 void popList(const IValueT Registers, CondARM32::Cond Cond); 245 void popList(const IValueT Registers, CondARM32::Cond Cond);
246 246
247 void push(const Operand *OpRt, CondARM32::Cond Cond); 247 void push(const Operand *OpRt, CondARM32::Cond Cond);
248 248
249 // Note: Registers is a bitset, where bit n corresponds to register Rn. 249 // Note: Registers is a bitset, where bit n corresponds to register Rn.
250 void pushList(const IValueT Registers, CondARM32::Cond Cond); 250 void pushList(const IValueT Registers, CondARM32::Cond Cond);
251 251
252 void rsb(const Operand *OpRd, const Operand *OpRn, const Operand *OpSrc1,
253 bool SetFlags, CondARM32::Cond Cond);
254
252 void sbc(const Operand *OpRd, const Operand *OpRn, const Operand *OpSrc1, 255 void sbc(const Operand *OpRd, const Operand *OpRn, const Operand *OpSrc1,
253 bool SetFlags, CondARM32::Cond Cond); 256 bool SetFlags, CondARM32::Cond Cond);
254 257
255 void sdiv(const Operand *OpRd, const Operand *OpRn, const Operand *OpSrc1, 258 void sdiv(const Operand *OpRd, const Operand *OpRn, const Operand *OpSrc1,
256 CondARM32::Cond Cond); 259 CondARM32::Cond Cond);
257 260
258 void str(const Operand *OpRt, const Operand *OpAddress, CondARM32::Cond Cond, 261 void str(const Operand *OpRt, const Operand *OpAddress, CondARM32::Cond Cond,
259 const TargetInfo &TInfo); 262 const TargetInfo &TInfo);
260 263
261 void str(const Operand *OpRt, const Operand *OpAddress, CondARM32::Cond Cond, 264 void str(const Operand *OpRt, const Operand *OpAddress, CondARM32::Cond Cond,
(...skipping 135 matching lines...) Expand 10 before | Expand all | Expand 10 after
397 // where cccc=Cond, xxxxxxx<<21=Opcode, dddd=Rd, s=SetFlags, and 400 // where cccc=Cond, xxxxxxx<<21=Opcode, dddd=Rd, s=SetFlags, and
398 // iiiiiiiiiiiiiiii=Imm16. 401 // iiiiiiiiiiiiiiii=Imm16.
399 void emitMovwt(CondARM32::Cond Cond, bool IsMovw, const Operand *OpRd, 402 void emitMovwt(CondARM32::Cond Cond, bool IsMovw, const Operand *OpRd,
400 const Operand *OpSrc, const char *MovName); 403 const Operand *OpSrc, const char *MovName);
401 }; 404 };
402 405
403 } // end of namespace ARM32 406 } // end of namespace ARM32
404 } // end of namespace Ice 407 } // end of namespace Ice
405 408
406 #endif // SUBZERO_SRC_ICEASSEMBLERARM32_H 409 #endif // SUBZERO_SRC_ICEASSEMBLERARM32_H
OLDNEW
« no previous file with comments | « src/DartARM32/assembler_arm.cc ('k') | src/IceAssemblerARM32.cpp » ('j') | no next file with comments »

Powered by Google App Engine
This is Rietveld 408576698