Add RSB instruction to the ARM integrated assembler.

src/IceAssemblerARM32.cpp

 //===- subzero/src/IceAssemblerARM32.cpp - Assembler for ARM32 --*- C++ -*-===//
 //
 // Copyright (c) 2013, the Dart project authors.  Please see the AUTHORS file
 // for details. All rights reserved. Use of this source code is governed by a
 // BSD-style license that can be found in the LICENSE file.
 //
 // Modified by the Subzero authors.
 //
 //===----------------------------------------------------------------------===//
 //
@@ skipping 1459 matching lines @@
   IValueT Rm = encodeRegister(OpSrc1, "Rm", MulName);
   verifyRegNotPc(Rd, "Rd", MulName);
   verifyRegNotPc(Rn, "Rn", MulName);
   verifyRegNotPc(Rm, "Rm", MulName);
   // Assembler registers rd, rn, rm are encoded as rn, rm, rs.
   constexpr IValueT MulOpcode = 0;
   emitMulOp(Cond, MulOpcode, RegARM32::Encoded_Reg_r0, Rd, Rn, Rm, SetFlags,
             MulName);
 }
 
-void AssemblerARM32::udiv(const Operand *OpRd, const Operand *OpRn,
-                          const Operand *OpSrc1, CondARM32::Cond Cond) {
-  // UDIV - ARM section A8.8.248, encoding A1.
-  //   udiv<c> <Rd>, <Rn>, <Rm>
+void AssemblerARM32::rsb(const Operand *OpRd, const Operand *OpRn,
+                         const Operand *OpSrc1, bool SetFlags,
+                         CondARM32::Cond Cond) {
+  // RSB (immediate) - ARM section A8.8.152, encoding A1.
+  //   rsb{s}<c> <Rd>, <Rn>, #<RotatedImm8>
   //
-  // cccc01110011dddd1111mmmm0001nnnn where cccc=Cond, dddd=Rd, nnnn=Rn, and
-  // mmmm=Rm.
-  constexpr const char *UdivName = "udiv";
-  IValueT Rd = encodeRegister(OpRd, "Rd", UdivName);
-  IValueT Rn = encodeRegister(OpRn, "Rn", UdivName);
-  IValueT Rm = encodeRegister(OpSrc1, "Rm", UdivName);
-  verifyRegNotPc(Rd, "Rd", UdivName);
-  verifyRegNotPc(Rn, "Rn", UdivName);
-  verifyRegNotPc(Rm, "Rm", UdivName);
-  // Assembler registers rd, rn, rm are encoded as rn, rm, rs.
-  constexpr IValueT UdivOpcode = B21;
-  emitDivOp(Cond, UdivOpcode, Rd, Rn, Rm, UdivName);
+  // cccc0010011snnnnddddiiiiiiiiiiii where cccc=Cond, dddd=Rd, nnnn=Rn,
+  // s=setFlags and iiiiiiiiiiii defines the RotatedImm8 value.
+  //
+  // RSB (register) - ARM section A8.8.163, encoding A1.
+  //   rsb{s}<c> <Rd>, <Rn>, <Rm>{, <Shift>}
+  //
+  // cccc0000011snnnnddddiiiiitt0mmmm where cccc=Cond, dddd=Rd, nnnn=Rn,
+  // mmmm=Rm, iiiii=shift, tt==ShiftKind, and s=SetFlags.
+  constexpr const char *RsbName = "rsb";
+  constexpr IValueT RsbOpcode = B1 | B0; // 0011
+  emitType01(Cond, RsbOpcode, OpRd, OpRn, OpSrc1, SetFlags, RdIsPcAndSetFlags,
+             RsbName);
 }
 
 void AssemblerARM32::sub(const Operand *OpRd, const Operand *OpRn,
                          const Operand *OpSrc1, bool SetFlags,
                          CondARM32::Cond Cond) {
   // SUB (register) - ARM section A8.8.223, encoding A1:
   //   sub{s}<c> <Rd>, <Rn>, <Rm>{, <shift>}
   // SUB (SP minus register): See ARM section 8.8.226, encoding A1:
   //   sub{s}<c> <Rd>, sp, <Rm>{, <Shift>}
   //
   // cccc0000010snnnnddddiiiiitt0mmmm where cccc=Cond, dddd=Rd, nnnn=Rn,
-  // mmmm=Rm, iiiiii=shift, tt=ShiftKind, and s=SetFlags.
+  // mmmm=Rm, iiiii=shift, tt=ShiftKind, and s=SetFlags.
   //
   // Sub (Immediate) - ARM section A8.8.222, encoding A1:
   //    sub{s}<c> <Rd>, <Rn>, #<RotatedImm8>
   // Sub (Sp minus immediate) - ARM section A8.*.225, encoding A1:
   //    sub{s}<c> sp, <Rn>, #<RotatedImm8>
   //
   // cccc0010010snnnnddddiiiiiiiiiiii where cccc=Cond, dddd=Rd, nnnn=Rn,
   // s=SetFlags and iiiiiiiiiiii=Src1Value defining RotatedImm8
   constexpr const char *SubName = "sub";
   constexpr IValueT SubOpcode = B1; // 0010
@@ skipping 12 matching lines @@
   // TST (immediate) - ARM section A8.8.240, encoding A1:
   //   tst<c> <Rn>, #<RotatedImm8>
   //
   // cccc00110001nnnn0000iiiiiiiiiiii where cccc=Cond, nnnn=Rn, and
   // iiiiiiiiiiii defines RotatedImm8.
   constexpr const char *TstName = "tst";
   constexpr IValueT TstOpcode = B3; // ie. 1000
   emitCompareOp(Cond, TstOpcode, OpRn, OpSrc1, TstName);
 }
 
+void AssemblerARM32::udiv(const Operand *OpRd, const Operand *OpRn,
+                          const Operand *OpSrc1, CondARM32::Cond Cond) {
+  // UDIV - ARM section A8.8.248, encoding A1.
+  //   udiv<c> <Rd>, <Rn>, <Rm>
+  //
+  // cccc01110011dddd1111mmmm0001nnnn where cccc=Cond, dddd=Rd, nnnn=Rn, and
+  // mmmm=Rm.
+  constexpr const char *UdivName = "udiv";
+  IValueT Rd = encodeRegister(OpRd, "Rd", UdivName);
+  IValueT Rn = encodeRegister(OpRn, "Rn", UdivName);
+  IValueT Rm = encodeRegister(OpSrc1, "Rm", UdivName);
+  verifyRegNotPc(Rd, "Rd", UdivName);
+  verifyRegNotPc(Rn, "Rn", UdivName);
+  verifyRegNotPc(Rm, "Rm", UdivName);
+  // Assembler registers rd, rn, rm are encoded as rn, rm, rs.
+  constexpr IValueT UdivOpcode = B21;
+  emitDivOp(Cond, UdivOpcode, Rd, Rn, Rm, UdivName);
+}
+
 void AssemblerARM32::umull(const Operand *OpRdLo, const Operand *OpRdHi,
                            const Operand *OpRn, const Operand *OpRm,
                            CondARM32::Cond Cond) {
   // UMULL - ARM section A8.8.257, encoding A1:
   //   umull<c> <RdLo>, <RdHi>, <Rn>, <Rm>
   //
   // cccc0000100shhhhllllmmmm1001nnnn where hhhh=RdHi, llll=RdLo, nnnn=Rn,
   // mmmm=Rm, and s=SetFlags
   constexpr const char *UmullName = "umull";
   IValueT RdLo = encodeRegister(OpRdLo, "RdLo", UmullName);
@@ skipping 39 matching lines @@
     // rr defined (RotationValue) rotate.
     constexpr IValueT UxtOpcode = B26 | B25 | B23 | B22 | B21 | B20;
     emitUxt(Cond, UxtOpcode, Rd, Rn, Rm, Rotation, UxtName);
     return;
   }
   }
 }
 
 } // end of namespace ARM32
 } // end of namespace Ice