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1 // Copyright (c) 2013, the Dart project authors. Please see the AUTHORS file | 1 // Copyright (c) 2013, the Dart project authors. Please see the AUTHORS file |
2 // for details. All rights reserved. Use of this source code is governed by a | 2 // for details. All rights reserved. Use of this source code is governed by a |
3 // BSD-style license that can be found in the LICENSE file. | 3 // BSD-style license that can be found in the LICENSE file. |
4 // | 4 // |
5 // This is forked from Dart revision df52deea9f25690eb8b66c5995da92b70f7ac1fe | 5 // This is forked from Dart revision df52deea9f25690eb8b66c5995da92b70f7ac1fe |
6 // Please update the (git) revision if we merge changes from Dart. | 6 // Please update the (git) revision if we merge changes from Dart. |
7 // https://code.google.com/p/dart/wiki/GettingTheSource | 7 // https://code.google.com/p/dart/wiki/GettingTheSource |
8 | 8 |
9 #include "vm/globals.h" // NOLINT | 9 #include "vm/globals.h" // NOLINT |
10 #if defined(TARGET_ARCH_ARM) | 10 #if defined(TARGET_ARCH_ARM) |
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195 | 195 |
196 // Moved to ARM32::AssemberARM32::eor() | 196 // Moved to ARM32::AssemberARM32::eor() |
197 void Assembler::eor(Register rd, Register rn, Operand o, Condition cond) { | 197 void Assembler::eor(Register rd, Register rn, Operand o, Condition cond) { |
198 EmitType01(cond, o.type(), EOR, 0, rn, rd, o); | 198 EmitType01(cond, o.type(), EOR, 0, rn, rd, o); |
199 } | 199 } |
200 | 200 |
201 // Moved to ARM32::AssemberARM32::sub() | 201 // Moved to ARM32::AssemberARM32::sub() |
202 void Assembler::sub(Register rd, Register rn, Operand o, Condition cond) { | 202 void Assembler::sub(Register rd, Register rn, Operand o, Condition cond) { |
203 EmitType01(cond, o.type(), SUB, 0, rn, rd, o); | 203 EmitType01(cond, o.type(), SUB, 0, rn, rd, o); |
204 } | 204 } |
205 #endif | |
206 | 205 |
| 206 // Moved to ARM32::AssemberARM32::rsb() |
207 void Assembler::rsb(Register rd, Register rn, Operand o, Condition cond) { | 207 void Assembler::rsb(Register rd, Register rn, Operand o, Condition cond) { |
208 EmitType01(cond, o.type(), RSB, 0, rn, rd, o); | 208 EmitType01(cond, o.type(), RSB, 0, rn, rd, o); |
209 } | 209 } |
210 | 210 |
| 211 // Moved to ARM32::AssemberARM32::rsb() |
211 void Assembler::rsbs(Register rd, Register rn, Operand o, Condition cond) { | 212 void Assembler::rsbs(Register rd, Register rn, Operand o, Condition cond) { |
212 EmitType01(cond, o.type(), RSB, 1, rn, rd, o); | 213 EmitType01(cond, o.type(), RSB, 1, rn, rd, o); |
213 } | 214 } |
214 | 215 |
215 #if 0 | |
216 // Moved to ARM32::AssemberARM32::add() | 216 // Moved to ARM32::AssemberARM32::add() |
217 void Assembler::add(Register rd, Register rn, Operand o, Condition cond) { | 217 void Assembler::add(Register rd, Register rn, Operand o, Condition cond) { |
218 EmitType01(cond, o.type(), ADD, 0, rn, rd, o); | 218 EmitType01(cond, o.type(), ADD, 0, rn, rd, o); |
219 } | 219 } |
220 | 220 |
221 // Moved to ARM32::AssemberARM32::add() | 221 // Moved to ARM32::AssemberARM32::add() |
222 void Assembler::adds(Register rd, Register rn, Operand o, Condition cond) { | 222 void Assembler::adds(Register rd, Register rn, Operand o, Condition cond) { |
223 EmitType01(cond, o.type(), ADD, 1, rn, rd, o); | 223 EmitType01(cond, o.type(), ADD, 1, rn, rd, o); |
224 } | 224 } |
225 | 225 |
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3686 | 3686 |
3687 | 3687 |
3688 const char* Assembler::FpuRegisterName(FpuRegister reg) { | 3688 const char* Assembler::FpuRegisterName(FpuRegister reg) { |
3689 ASSERT((0 <= reg) && (reg < kNumberOfFpuRegisters)); | 3689 ASSERT((0 <= reg) && (reg < kNumberOfFpuRegisters)); |
3690 return fpu_reg_names[reg]; | 3690 return fpu_reg_names[reg]; |
3691 } | 3691 } |
3692 | 3692 |
3693 } // namespace dart | 3693 } // namespace dart |
3694 | 3694 |
3695 #endif // defined TARGET_ARCH_ARM | 3695 #endif // defined TARGET_ARCH_ARM |
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