Subzero. ARM32. Initial sandboxing code.

src/IceTargetLoweringARM32.h

 //===- subzero/src/IceTargetLoweringARM32.h - ARM32 lowering ----*- C++ -*-===//
 //
 //                        The Subzero Code Generator
 //
 // This file is distributed under the University of Illinois Open Source
 // License. See LICENSE.TXT for details.
 //
 //===----------------------------------------------------------------------===//
 ///
 /// \file
@@ skipping 144 matching lines @@
                     int32_t RegNum = Variable::NoRegister);
   Variable *legalizeToReg(Operand *From, int32_t RegNum = Variable::NoRegister);
 
   OperandARM32ShAmtImm *shAmtImm(uint32_t ShAmtImm) const {
     assert(ShAmtImm < 32);
     return OperandARM32ShAmtImm::create(
         Func,
         llvm::cast<ConstantInteger32>(Ctx->getConstantInt32(ShAmtImm & 0x1F)));
   }
 
+  OperandARM32FlexImm *indirectBranchBicMask() const {
+    constexpr uint32_t Imm8 = 0xFC; // 0xC000000F
+    constexpr uint32_t RotateAmt = 2;
+    return OperandARM32FlexImm::create(Func, IceType_i32, Imm8, RotateAmt);
+  }
+
+  OperandARM32FlexImm *memOpBicMask() const {
+    constexpr uint32_t Imm8 = 0x0C; // 0xC0000000
+    constexpr uint32_t RotateAmt = 2;
+    return OperandARM32FlexImm::create(Func, IceType_i32, Imm8, RotateAmt);
+  }
+
   GlobalContext *getCtx() const { return Ctx; }
 
 protected:
   explicit TargetARM32(Cfg *Func);
 
   void postLower() override;
 
   enum SafeBoolChain {
     SBC_No,
     SBC_Yes,
@@ skipping 640 matching lines @@
   // TODO(jpp): This could live in the Parser, if we provided a Target-specific
   // method that the Parser could call.
   void findMaxStackOutArgsSize();
 
   /// Returns true if the given Offset can be represented in a Load/Store Mem
   /// Operand.
   bool isLegalMemOffset(Type Ty, int32_t Offset) const;
 
   void postLowerLegalization();
 
+  class AutoSandboxer {
+  public:
+    explicit AutoSandboxer(
+        TargetARM32 *Target,
+        InstBundleLock::Option BundleOption = InstBundleLock::Opt_None)
+        : Target(Target) {
+      if (Target->NeedSandboxing) {
+        Target->_bundle_lock(BundleOption);
+      }
+    }
+
+    void add_sp(Operand *AddAmount) {
+      Variable *SP = Target->getPhysicalRegister(RegARM32::Reg_sp);
+      Target->_add(SP, SP, AddAmount);
+      if (Target->NeedSandboxing) {
+        Target->_bic(SP, SP, Target->memOpBicMask());
+      }
+    }
+
+    void align_sp(size_t Alignment) {
+      Variable *SP = Target->getPhysicalRegister(RegARM32::Reg_sp);
+      Target->alignRegisterPow2(SP, Alignment);
+      if (Target->NeedSandboxing) {
+        Target->_bic(SP, SP, Target->memOpBicMask());
+      }
+    }
+
+    InstARM32Call *bl(Variable *ReturnReg, Operand *CallTarget) {
+      if (Target->NeedSandboxing) {
+        if (auto *CallTargetR = llvm::dyn_cast<Variable>(CallTarget)) {
+          Target->_bic(CallTargetR, CallTargetR,
+                       Target->indirectBranchBicMask());
+        }
+      }
+      auto *Call = InstARM32Call::create(Target->Func, ReturnReg, CallTarget);
+      Target->Context.insert(Call);
+      return Call;
+    }
+
+    void ldr(Variable *Dest, OperandARM32Mem *Mem, CondARM32::Cond Pred) {
+      if (Target->NeedSandboxing) {
+        assert(!Mem->isRegReg());
+        Variable *MemBase = Mem->getBase();
+        Target->_bic(MemBase, MemBase, Target->memOpBicMask(), Pred);
+      }
+      Target->_ldr(Dest, Mem, Pred);
+    }
+
+    void ldrex(Variable *Dest, OperandARM32Mem *Mem, CondARM32::Cond Pred) {
+      if (Target->NeedSandboxing) {
+        assert(!Mem->isRegReg());
+        Variable *MemBase = Mem->getBase();
+        Target->_bic(MemBase, MemBase, Target->memOpBicMask(), Pred);
+      }
+      Target->_ldrex(Dest, Mem, Pred);
+    }
+
+    void reset_sp(Variable *Src) {
+      Variable *SP = Target->getPhysicalRegister(RegARM32::Reg_sp);
+      Target->_mov_redefined(SP, Src);
+      if (Target->NeedSandboxing) {
+        Target->_bic(SP, SP, Target->memOpBicMask());
+      }
+    }
+
+    void ret(Variable *RetAddr, Variable *RetValue) {
+      if (Target->NeedSandboxing) {
+        Target->_bic(RetAddr, RetAddr, Target->indirectBranchBicMask());
+      }
+      Target->_ret(RetAddr, RetValue);
+    }
+
+    void str(Variable *Src, OperandARM32Mem *Mem, CondARM32::Cond Pred) {
+      if (Target->NeedSandboxing) {
+        assert(!Mem->isRegReg());
+        Variable *MemBase = Mem->getBase();
+        Target->_bic(MemBase, MemBase, Target->memOpBicMask(), Pred);
+      }
+      Target->_str(Src, Mem, Pred);
+    }
+
+    void strex(Variable *Dest, Variable *Src, OperandARM32Mem *Mem,
+               CondARM32::Cond Pred) {
+      if (Target->NeedSandboxing) {
+        assert(!Mem->isRegReg());
+        Variable *MemBase = Mem->getBase();
+        Target->_bic(MemBase, MemBase, Target->memOpBicMask(), Pred);
+      }
+      Target->_strex(Dest, Src, Mem, Pred);
+    }
+
+    void sub_sp(Operand *SubAmount) {
+      Variable *SP = Target->getPhysicalRegister(RegARM32::Reg_sp);
+      Target->_sub(SP, SP, SubAmount);
+      if (Target->NeedSandboxing) {
+        Target->_bic(SP, SP, Target->memOpBicMask());
+      }
+    }
+
+    ~AutoSandboxer() {
+      if (Target->NeedSandboxing) {
+        Target->_bundle_unlock();
+      }
+    }
+
+  private:
+    TargetARM32 *Target;
+  };
+
   class PostLoweringLegalizer {
     PostLoweringLegalizer() = delete;
     PostLoweringLegalizer(const PostLoweringLegalizer &) = delete;
     PostLoweringLegalizer &operator=(const PostLoweringLegalizer &) = delete;
 
   public:
     explicit PostLoweringLegalizer(TargetARM32 *Target)
         : Target(Target), StackOrFrameReg(Target->getPhysicalRegister(
                               Target->getFrameOrStackReg())) {}
 
@@ skipping 36 matching lines @@
     /// a new base register ip=Base+Offset is created, and the method returns a
     /// memory operand expressing [ip, #0].
     OperandARM32Mem *createMemOperand(Type Ty, Variable *Base, int32_t Offset,
                                       bool AllowOffsets = true);
     TargetARM32 *const Target;
     Variable *const StackOrFrameReg;
     Variable *TempBaseReg = nullptr;
     int32_t TempBaseOffset = 0;
   };
 
+  const bool NeedSandboxing;
   TargetARM32Features CPUFeatures;
   bool UsesFramePointer = false;
   bool NeedsStackAlignment = false;
   bool MaybeLeafFunc = true;
   size_t SpillAreaSizeBytes = 0;
   size_t FixedAllocaSizeBytes = 0;
   size_t FixedAllocaAlignBytes = 0;
   bool PrologEmitsFixedAllocas = false;
   uint32_t MaxOutArgsSizeBytes = 0;
   // TODO(jpp): std::array instead of array.
@@ skipping 185 matching lines @@
 
 private:
   ~TargetHeaderARM32() = default;
 
   TargetARM32Features CPUFeatures;
 };
 
 } // end of namespace Ice
 
 #endif // SUBZERO_SRC_ICETARGETLOWERINGARM32_H