Clean up use of encode/decode in the ARM integrated assembler.

src/IceAssemblerARM32.cpp

 //===- subzero/src/IceAssemblerARM32.cpp - Assembler for ARM32 --*- C++ -*-===//
 //
 // Copyright (c) 2013, the Dart project authors.  Please see the AUTHORS file
 // for details. All rights reserved. Use of this source code is governed by a
 // BSD-style license that can be found in the LICENSE file.
 //
 // Modified by the Subzero authors.
 //
 //===----------------------------------------------------------------------===//
 //
@@ skipping 159 matching lines @@
 // Extract out a Bit in Value.
 inline bool isBitSet(IValueT Bit, IValueT Value) {
   return (Value & Bit) == Bit;
 }
 
 // Returns the GPR register at given Shift in Value.
 inline RegARM32::GPRRegister getGPRReg(IValueT Shift, IValueT Value) {
   return decodeGPRRegister((Value >> Shift) & 0xF);
 }
 
-// The way an operand was decoded in functions decodeOperand and decodeAddress
-// below.
-enum DecodedResult {
-  // Unable to decode, value left undefined.
-  CantDecode = 0,
+// The way an operand is encoded into a sequence of bits in functions
+// encodeOperand and encodeAddress below.
+enum EncodedOperand {
+  // Unable to encode, value left undefined.
+  CantEncode = 0,
   // Value is register found.
-  DecodedAsRegister,
+  EncodedAsRegister,
   // Value=rrrriiiiiiii where rrrr is the rotation, and iiiiiiii is the imm8
   // value.
-  DecodedAsRotatedImm8,
+  EncodedAsRotatedImm8,
   // Value=0000000pu0w0nnnn0000iiiiiiiiiiii where nnnn is the base register Rn,
   // p=1 if pre-indexed addressing, u=1 if offset positive, w=1 if writeback to
   // Rn should be used, and iiiiiiiiiiii defines the rotated Imm8 value.
-  DecodedAsImmRegOffset,
+  EncodedAsImmRegOffset,
   // Value=00000000pu0w0nnnn0000iiii0000jjjj where nnnn=Rn, iiiijjjj=Imm8, p=1
   // if pre-indexed addressing, u=1 if offset positive, and w=1 if writeback to
   // Rn.
-  DecodedAsImmRegOffsetEnc3,
+  EncodedAsImmRegOffsetEnc3,
   // Value=0000000pu0w00nnnnttttiiiiiss0mmmm where nnnn is the base register Rn,
   // mmmm is the index register Rm, iiiii is the shift amount, ss is the shift
   // kind, p=1 if pre-indexed addressing, u=1 if offset positive, and w=1 if
   // writeback to Rn.
-  DecodedAsShiftRotateImm5,
+  EncodedAsShiftRotateImm5,
   // Value=000000000000000000000iiiii0000000 where iiii defines the Imm5 value
   // to shift.
-  DecodedAsShiftImm5,
+  EncodedAsShiftImm5,
   // i.e. iiiiiss0mmmm where mmmm is the register to rotate, ss is the shift
   // kind, and iiiii is the shift amount.
-  DecodedAsShiftedRegister,
+  EncodedAsShiftedRegister,
   // Value is 32bit integer constant.
-  DecodedAsConstI32
+  EncodedAsConstI32
 };
 
 // Sets Encoding to a rotated Imm8 encoding of Value, if possible.
 inline IValueT encodeRotatedImm8(IValueT RotateAmt, IValueT Immed8) {
   assert(RotateAmt < (1 << kRotateBits));
   assert(Immed8 < (1 << kImmed8Bits));
   return (RotateAmt << kRotateShift) | (Immed8 << kImmed8Shift);
 }
 
 // Encodes iiiiitt0mmmm for data-processing (2nd) operands where iiiii=Imm5,
 // tt=Shift, and mmmm=Rm.
 IValueT encodeShiftRotateImm5(IValueT Rm, OperandARM32::ShiftKind Shift,
                               IOffsetT imm5) {
   (void)kShiftImmBits;
   assert(imm5 < (1 << kShiftImmBits));
   return (imm5 << kShiftImmShift) | (encodeShift(Shift) << kShiftShift) | Rm;
 }
 
 // Encodes mmmmtt01ssss for data-processing operands where mmmm=Rm, ssss=Rs, and
 // tt=Shift.
 IValueT encodeShiftRotateReg(IValueT Rm, OperandARM32::ShiftKind Shift,
                              IValueT Rs) {
   return (Rs << kRsShift) | (encodeShift(Shift) << kShiftShift) | B4 |
          (Rm << kRmShift);
 }
 
-DecodedResult decodeOperand(const Operand *Opnd, IValueT &Value) {
+EncodedOperand encodeOperand(const Operand *Opnd, IValueT &Value) {
   Value = 0; // Make sure initialized.
   if (const auto *Var = llvm::dyn_cast<Variable>(Opnd)) {
     if (Var->hasReg()) {
       Value = Var->getRegNum();
-      return DecodedAsRegister;
+      return EncodedAsRegister;
     }
-    return CantDecode;
+    return CantEncode;
   }
   if (const auto *FlexImm = llvm::dyn_cast<OperandARM32FlexImm>(Opnd)) {
     const IValueT Immed8 = FlexImm->getImm();
     const IValueT Rotate = FlexImm->getRotateAmt();
     if (!((Rotate < (1 << kRotateBits)) && (Immed8 < (1 << kImmed8Bits))))
-      return CantDecode;
+      return CantEncode;
     Value = (Rotate << kRotateShift) | (Immed8 << kImmed8Shift);
-    return DecodedAsRotatedImm8;
+    return EncodedAsRotatedImm8;
   }
   if (const auto *Const = llvm::dyn_cast<ConstantInteger32>(Opnd)) {
     Value = Const->getValue();
-    return DecodedAsConstI32;
+    return EncodedAsConstI32;
   }
   if (const auto *FlexReg = llvm::dyn_cast<OperandARM32FlexReg>(Opnd)) {
     Operand *Amt = FlexReg->getShiftAmt();
     if (const auto *Imm5 = llvm::dyn_cast<OperandARM32ShAmtImm>(Amt)) {
       IValueT Rm;
-      if (decodeOperand(FlexReg->getReg(), Rm) != DecodedAsRegister)
-        return CantDecode;
+      if (encodeOperand(FlexReg->getReg(), Rm) != EncodedAsRegister)
+        return CantEncode;
       Value =
           encodeShiftRotateImm5(Rm, FlexReg->getShiftOp(), Imm5->getShAmtImm());
-      return DecodedAsShiftedRegister;
+      return EncodedAsShiftedRegister;
     }
     // TODO(kschimpf): Handle case where Amt is a register?
   }
   if (const auto *ShImm = llvm::dyn_cast<OperandARM32ShAmtImm>(Opnd)) {
     const IValueT Immed5 = ShImm->getShAmtImm();
     assert(Immed5 < (1 << kShiftImmBits));
     Value = (Immed5 << kShiftImmShift);
-    return DecodedAsShiftImm5;
+    return EncodedAsShiftImm5;
   }
-  return CantDecode;
+  return CantEncode;
 }
 
 IValueT encodeImmRegOffset(IValueT Reg, IOffsetT Offset,
                            OperandARM32Mem::AddrMode Mode) {
   IValueT Value = Mode | (Reg << kRnShift);
   if (Offset < 0) {
     Value = (Value ^ U) | -Offset; // Flip U to adjust sign.
   } else {
     Value |= Offset;
   }
@@ skipping 15 matching lines @@
 
 // Defines alternate layouts of instruction operands, should the (common)
 // default pattern not be used.
 enum OpEncoding {
   // No alternate layout specified.
   DefaultOpEncoding,
   // Alternate encoding 3.
   OpEncoding3
 };
 
-// Decodes memory address Opnd, and encodes that information into Value,
-// based on how ARM represents the address. Returns how the value was encoded.
-DecodedResult decodeAddress(const Operand *Opnd, IValueT &Value,
-                            const AssemblerARM32::TargetInfo &TInfo,
-                            OpEncoding AddressEncoding = DefaultOpEncoding) {
+// Encodes memory address Opnd, and encodes that information into Value, based
+// on how ARM represents the address. Returns how the value was encoded.
+EncodedOperand encodeAddress(const Operand *Opnd, IValueT &Value,
+                             const AssemblerARM32::TargetInfo &TInfo,
+                             OpEncoding AddressEncoding = DefaultOpEncoding) {
   Value = 0; // Make sure initialized.
   if (const auto *Var = llvm::dyn_cast<Variable>(Opnd)) {
     // Should be a stack variable, with an offset.
     if (Var->hasReg())
-      return CantDecode;
+      return CantEncode;
     IOffsetT Offset = Var->getStackOffset();
     if (!Utils::IsAbsoluteUint(12, Offset))
-      return CantDecode;
+      return CantEncode;
     int32_t BaseRegNum = Var->getBaseRegNum();
     if (BaseRegNum == Variable::NoRegister)
       BaseRegNum = TInfo.FrameOrStackReg;
     Value = encodeImmRegOffset(BaseRegNum, Offset, OperandARM32Mem::Offset);
-    return DecodedAsImmRegOffset;
+    return EncodedAsImmRegOffset;
   }
   if (const auto *Mem = llvm::dyn_cast<OperandARM32Mem>(Opnd)) {
     Variable *Var = Mem->getBase();
     if (!Var->hasReg())
-      return CantDecode;
+      return CantEncode;
     IValueT Rn = Var->getRegNum();
     if (Mem->isRegReg()) {
       const Variable *Index = Mem->getIndex();
       if (Var == nullptr)
-        return CantDecode;
+        return CantEncode;
       Value = (Rn << kRnShift) | Mem->getAddrMode() |
               encodeShiftRotateImm5(Index->getRegNum(), Mem->getShiftOp(),
                                     Mem->getShiftAmt());
-      return DecodedAsShiftRotateImm5;
+      return EncodedAsShiftRotateImm5;
     }
-    // Decoded as immediate register offset.
+    // Encoded as immediate register offset.
     ConstantInteger32 *Offset = Mem->getOffset();
     switch (AddressEncoding) {
     case DefaultOpEncoding:
       Value = encodeImmRegOffset(Rn, Offset->getValue(), Mem->getAddrMode());
-      return DecodedAsImmRegOffset;
+      return EncodedAsImmRegOffset;
     case OpEncoding3:
       Value =
           encodeImmRegOffsetEnc3(Rn, Offset->getValue(), Mem->getAddrMode());
-      return DecodedAsImmRegOffsetEnc3;
+      return EncodedAsImmRegOffsetEnc3;
     }
   }
-  return CantDecode;
+  return CantEncode;
 }
 
 // Checks that Offset can fit in imm24 constant of branch (b) instruction.
 bool canEncodeBranchOffset(IOffsetT Offset) {
   return Utils::IsAligned(Offset, 4) &&
          Utils::IsInt(kBranchOffsetBits, Offset >> 2);
 }
 
 } // end of anonymous namespace
 
@@ skipping 86 matching lines @@
   assert(IsGoodOffset);
   // Note: Following cast is for MINIMAL build.
   (void)IsGoodOffset;
 
   // Properly preserve only the bits supported in the instruction.
   Offset >>= 2;
   Offset &= kBranchOffsetMask;
   return (Inst & ~kBranchOffsetMask) | Offset;
 }
 
+// Pull out offset from branch Inst.
 IOffsetT AssemblerARM32::decodeBranchOffset(IValueT Inst) {
   // Sign-extend, left-shift by 2, and adjust to the way ARM CPUs read PC.
   IOffsetT Offset = static_cast<IOffsetT>((Inst & kBranchOffsetMask) << 8);
   return (Offset >> 6) + kPCReadOffset;
 }
 
 void AssemblerARM32::bind(Label *L) {
   IOffsetT BoundPc = Buffer.size();
   assert(!L->isBound()); // Labels can only be bound once.
   while (L->isLinked()) {
@@ skipping 37 matching lines @@
                            (encodeBool(SetFlags) << kSShift) |
                            (Rn << kRnShift) | (Rd << kRdShift) | Imm12;
   emitInst(Encoding);
 }
 
 void AssemblerARM32::emitType01(IValueT Opcode, const Operand *OpRd,
                                 const Operand *OpRn, const Operand *OpSrc1,
                                 bool SetFlags, CondARM32::Cond Cond,
                                 EmitChecks RuleChecks) {
   IValueT Rd;
-  if (decodeOperand(OpRd, Rd) != DecodedAsRegister)
+  if (encodeOperand(OpRd, Rd) != EncodedAsRegister)
     return setNeedsTextFixup();
   IValueT Rn;
-  if (decodeOperand(OpRn, Rn) != DecodedAsRegister)
+  if (encodeOperand(OpRn, Rn) != EncodedAsRegister)
     return setNeedsTextFixup();
   emitType01(Opcode, Rd, Rn, OpSrc1, SetFlags, Cond, RuleChecks);
 }
 
 void AssemblerARM32::emitType01(IValueT Opcode, IValueT Rd, IValueT Rn,
                                 const Operand *OpSrc1, bool SetFlags,
                                 CondARM32::Cond Cond, EmitChecks RuleChecks) {
 
   IValueT Src1Value;
   // TODO(kschimpf) Other possible decodings of data operations.
-  switch (decodeOperand(OpSrc1, Src1Value)) {
+  switch (encodeOperand(OpSrc1, Src1Value)) {
   default:
     return setNeedsTextFixup();
-  case DecodedAsRegister: {
+  case EncodedAsRegister: {
     // XXX (register)
     //   xxx{s}<c> <Rd>, <Rn>, <Rm>{, <shiff>}
     //
     // cccc0000100snnnnddddiiiiitt0mmmm where cccc=Cond, dddd=Rd, nnnn=Rn,
     // mmmm=Rm, iiiii=Shift, tt=ShiftKind, and s=SetFlags.
     constexpr IValueT Imm5 = 0;
     Src1Value = encodeShiftRotateImm5(Src1Value, OperandARM32::kNoShift, Imm5);
     emitType01(Cond, kInstTypeDataRegister, Opcode, SetFlags, Rn, Rd, Src1Value,
                RuleChecks);
     return;
   }
-  case DecodedAsShiftedRegister: {
-    // Form is defined in case DecodedAsRegister. (i.e. XXX (register)).
+  case EncodedAsShiftedRegister: {
+    // Form is defined in case EncodedAsRegister. (i.e. XXX (register)).
     emitType01(Cond, kInstTypeDataRegister, Opcode, SetFlags, Rn, Rd, Src1Value,
                RuleChecks);
     return;
   }
-  case DecodedAsConstI32: {
+  case EncodedAsConstI32: {
     // See if we can convert this to an XXX (immediate).
     IValueT RotateAmt;
     IValueT Imm8;
     if (!OperandARM32FlexImm::canHoldImm(Src1Value, &RotateAmt, &Imm8))
       return setNeedsTextFixup();
     Src1Value = encodeRotatedImm8(RotateAmt, Imm8);
     // Intentionally fall to next case!
   }
-  case DecodedAsRotatedImm8: {
+  case EncodedAsRotatedImm8: {
     // XXX (Immediate)
     //   xxx{s}<c> <Rd>, <Rn>, #<RotatedImm8>
     //
     // cccc0010100snnnnddddiiiiiiiiiiii where cccc=Cond, dddd=Rd, nnnn=Rn,
     // s=SetFlags and iiiiiiiiiiii=Src1Value defining RotatedImm8.
     emitType01(Cond, kInstTypeDataImmediate, Opcode, SetFlags, Rn, Rd,
                Src1Value, RuleChecks);
     return;
   }
   }
@@ skipping 39 matching lines @@
   //
   // XXX (immediate)
   //  XXX<c> <Rn>, #<RotatedImm8>
   //
   // ccccyyyxxxx1nnnn0000iiiiiiiiiiii where cccc=Cond, dddd=Rd, nnnn=Rn,
   // yyy=kInstTypeDataImmdiate, xxxx=Opcode, and iiiiiiiiiiii=Src1Value
   // defining RotatedImm8.
   constexpr bool SetFlags = true;
   constexpr IValueT Rd = RegARM32::Encoded_Reg_r0;
   IValueT Rn;
-  if (decodeOperand(OpRn, Rn) != DecodedAsRegister)
+  if (encodeOperand(OpRn, Rn) != EncodedAsRegister)
     return setNeedsTextFixup();
   emitType01(Opcode, Rd, Rn, OpSrc1, SetFlags, Cond, NoChecks);
 }
 
 void AssemblerARM32::emitMemOp(CondARM32::Cond Cond, IValueT InstType,
                                bool IsLoad, bool IsByte, IValueT Rt,
                                IValueT Address) {
   if (!isGPRRegisterDefined(Rt) || !isConditionDefined(Cond))
     return setNeedsTextFixup();
   AssemblerBuffer::EnsureCapacity ensured(&Buffer);
   const IValueT Encoding = (encodeCondition(Cond) << kConditionShift) |
                            (InstType << kTypeShift) | (IsLoad ? L : 0) |
                            (IsByte ? B : 0) | (Rt << kRdShift) | Address;
   emitInst(Encoding);
 }
 
 void AssemblerARM32::emitMemOp(CondARM32::Cond Cond, bool IsLoad, bool IsByte,
                                IValueT Rt, const Operand *OpAddress,
                                const TargetInfo &TInfo) {
   IValueT Address;
-  switch (decodeAddress(OpAddress, Address, TInfo)) {
+  switch (encodeAddress(OpAddress, Address, TInfo)) {
   default:
     return setNeedsTextFixup();
-  case DecodedAsImmRegOffset: {
+  case EncodedAsImmRegOffset: {
     // XXX{B} (immediate):
     //   xxx{b}<c> <Rt>, [<Rn>{, #+/-<imm12>}]      ; p=1, w=0
     //   xxx{b}<c> <Rt>, [<Rn>], #+/-<imm12>        ; p=1, w=1
     //   xxx{b}<c> <Rt>, [<Rn>, #+/-<imm12>]!       ; p=0, w=1
     //
     // cccc010pubwlnnnnttttiiiiiiiiiiii where cccc=Cond, tttt=Rt, nnnn=Rn,
     // iiiiiiiiiiii=imm12, b=IsByte, pu0w<<21 is a BlockAddr, l=IsLoad, and
     // pu0w0nnnn0000iiiiiiiiiiii=Address.
     RegARM32::GPRRegister Rn = getGPRReg(kRnShift, Address);
 
     // Check if conditions of rules violated.
     if (Rn == RegARM32::Encoded_Reg_pc)
       return setNeedsTextFixup();
     if (!isBitSet(P, Address) && isBitSet(W, Address))
       return setNeedsTextFixup();
     if (!IsByte && (Rn == RegARM32::Encoded_Reg_sp) && !isBitSet(P, Address) &&
         isBitSet(U, Address) & !isBitSet(W, Address) &&
         (mask(Address, kImm12Shift, kImmed12Bits) == 0x8 /* 000000000100 */))
       return setNeedsTextFixup();
 
     return emitMemOp(Cond, kInstTypeMemImmediate, IsLoad, IsByte, Rt, Address);
   }
-  case DecodedAsShiftRotateImm5: {
+  case EncodedAsShiftRotateImm5: {
     // XXX{B} (register)
     //   xxx{b}<c> <Rt>, [<Rn>, +/-<Rm>{, <shift>}]{!}
     //   xxx{b}<c> <Rt>, [<Rn>], +/-<Rm>{, <shift>}
     //
     // cccc011pubwlnnnnttttiiiiiss0mmmm where cccc=Cond, tttt=Rt,
     // b=IsByte, U=1 if +, pu0b is a BlockAddr, l=IsLoad, and
     // pu0w0nnnn0000iiiiiss0mmmm=Address.
     RegARM32::GPRRegister Rn = getGPRReg(kRnShift, Address);
     RegARM32::GPRRegister Rm = getGPRReg(kRmShift, Address);
 
@@ skipping 15 matching lines @@
 
     return emitMemOp(Cond, kInstTypeRegisterShift, IsLoad, IsByte, Rt, Address);
   }
   }
 }
 
 void AssemblerARM32::emitMemOpEnc3(CondARM32::Cond Cond, IValueT Opcode,
                                    IValueT Rt, const Operand *OpAddress,
                                    const TargetInfo &TInfo) {
   IValueT Address;
-  switch (decodeAddress(OpAddress, Address, TInfo, OpEncoding3)) {
+  switch (encodeAddress(OpAddress, Address, TInfo, OpEncoding3)) {
   default:
     return setNeedsTextFixup();
-  case DecodedAsImmRegOffsetEnc3: {
+  case EncodedAsImmRegOffsetEnc3: {
     // XXXH (immediate)
     //   xxxh<c> <Rt>, [<Rn>{, #+-<Imm8>}]
     //   xxxh<c> <Rt>, [<Rn>, #+/-<Imm8>]
     //   xxxh<c> <Rt>, [<Rn>, #+/-<Imm8>]!
     //
     // cccc000pu0wxnnnnttttiiiiyyyyjjjj where cccc=Cond, nnnn=Rn, tttt=Rt,
     // iiiijjjj=Imm8, pu0w<<21 is a BlockAddr, x000000000000yyyy0000=Opcode,
     // and pu0w0nnnn0000iiii0000jjjj=Address.
     if (!isGPRRegisterDefined(Rt) || !isConditionDefined(Cond))
       return setNeedsTextFixup();
     if (!isBitSet(P, Address) && isBitSet(W, Address))
       return setNeedsTextFixup();
     if ((Rt == RegARM32::Encoded_Reg_pc) ||
         (isBitSet(W, Address) &&
          (getGPRReg(kRnShift, Address) == decodeGPRRegister(Rt))))
       return setNeedsTextFixup();
     const IValueT Encoding = (encodeCondition(Cond) << kConditionShift) |
                              Opcode | (Rt << kRdShift) | Address;
     AssemblerBuffer::EnsureCapacity ensured(&Buffer);
     return emitInst(Encoding);
   }
-  case DecodedAsShiftRotateImm5: {
+  case EncodedAsShiftRotateImm5: {
     // XXXH (register)
     //   xxxh<c> <Rt>, [<Rn>, +/-<Rm>]{!}
     //   xxxh<c> <Rt>, [<Rn>], +/-<Rm>
     //
     // cccc000pu0wxnnnntttt00001011mmmm where cccc=Cond, tttt=Rt, nnnn=Rn,
     // mmmm=Rm, pu0w<<21 is a BlockAddr, x000000000000yyyy0000=Opcode, and
     // pu0w0nnnn000000000000mmmm=Address.
     if (!isGPRRegisterDefined(Rt) || !isConditionDefined(Cond))
       return setNeedsTextFixup();
     if (!isBitSet(P, Address) && isBitSet(W, Address))
@@ skipping 170 matching lines @@
   // and iiiiiiiiiiiiiiiiiiiiiiii is the (encoded) Target to branch to.
   emitFixup(createBlFixup(Target));
   constexpr CondARM32::Cond Cond = CondARM32::AL;
   constexpr IValueT Immed = 0;
   constexpr bool Link = true;
   emitType05(Cond, Immed, Link);
 }
 
 void AssemblerARM32::blx(const Operand *Target) {
   IValueT Rm;
-  if (decodeOperand(Target, Rm) != DecodedAsRegister)
+  if (encodeOperand(Target, Rm) != EncodedAsRegister)
     return setNeedsTextFixup();
   // BLX (register) - ARM section A8.8.26, encoding A1:
   //   blx<c> <Rm>
   //
   // cccc000100101111111111110011mmmm where cccc=Cond (not currently allowed)
   // and mmmm=Rm.
   if (Rm == RegARM32::Encoded_Reg_pc)
     // Unpredictable.
     return setNeedsTextFixup();
   AssemblerBuffer::EnsureCapacity ensured(&Buffer);
@@ skipping 49 matching lines @@
   // cccc0010001snnnnddddiiiiiiiiiiii where cccc=Cond, dddd=Rd, nnnn=Rn,
   // s=SetFlags and iiiiiiiiiiii=Src1Value defining RotatedImm8.
   constexpr IValueT Eor = B0; // 0001
   emitType01(Eor, OpRd, OpRn, OpSrc1, SetFlags, Cond, RdIsPcAndSetFlags);
 }
 
 void AssemblerARM32::ldr(const Operand *OpRt, const Operand *OpAddress,
                          CondARM32::Cond Cond, const TargetInfo &TInfo) {
   constexpr bool IsLoad = true;
   IValueT Rt;
-  if (decodeOperand(OpRt, Rt) != DecodedAsRegister)
+  if (encodeOperand(OpRt, Rt) != EncodedAsRegister)
     return setNeedsTextFixup();
   const Type Ty = OpRt->getType();
   switch (typeWidthInBytesLog2(Ty)) {
   case 3:
   // LDRD is not implemented because target lowering handles i64 and double by
   // using two (32-bit) load instructions. Note: Intenionally drop to default
   // case.
   default:
     llvm::report_fatal_error(std::string("Type ") + typeString(Ty) +
                              " not implementable using ldr\n");
@@ skipping 54 matching lines @@
   }
   }
 }
 
 void AssemblerARM32::lsl(const Operand *OpRd, const Operand *OpRm,
                          const Operand *OpSrc1, bool SetFlags,
                          CondARM32::Cond Cond) {
   constexpr IValueT Lsl = B3 | B2 | B0; // 1101
   constexpr IValueT Rn = 0;             // Rn field is not used.
   IValueT Rd;
-  if (decodeOperand(OpRd, Rd) != DecodedAsRegister)
+  if (encodeOperand(OpRd, Rd) != EncodedAsRegister)
     return setNeedsTextFixup();
   IValueT Rm;
-  if (decodeOperand(OpRm, Rm) != DecodedAsRegister)
+  if (encodeOperand(OpRm, Rm) != EncodedAsRegister)
     return setNeedsTextFixup();
   IValueT Value;
-  switch (decodeOperand(OpSrc1, Value)) {
+  switch (encodeOperand(OpSrc1, Value)) {
   default:
     return setNeedsTextFixup();
-  case DecodedAsShiftImm5: {
+  case EncodedAsShiftImm5: {
     // LSL (immediate) - ARM section A8.8.94, encoding A1:
     //   lsl{s}<c> <Rd>, <Rm>, #imm5
     //
     // cccc0001101s0000ddddiiiii000mmmm where cccc=Cond, s=SetFlags, dddd=Rd,
     // iiiii=imm5, and mmmm=Rm.
     Value = Value | (Rm << kRmShift);
     emitType01(Cond, kInstTypeDataRegShift, Lsl, SetFlags, Rn, Rd, Value,
                RdIsPcAndSetFlags);
     return;
   }
-  case DecodedAsRegister: {
+  case EncodedAsRegister: {
     // LSL (register) - ARM section A8.8.95, encoding A1:
     //   lsl{S}<c> <Rd>, <Rm>, <Rs>
     //
     // cccc0001101s0000ddddssss0001mmmm where cccc=Cond, s=SetFlags, dddd=Rd,
     // mmmm=Rm, and ssss=Rs.
     IValueT Rs;
-    if (decodeOperand(OpSrc1, Rs) != DecodedAsRegister)
+    if (encodeOperand(OpSrc1, Rs) != EncodedAsRegister)
       return setNeedsTextFixup();
     if ((Rd == RegARM32::Encoded_Reg_pc) || (Rm == RegARM32::Encoded_Reg_pc) ||
         (Rs == RegARM32::Encoded_Reg_pc))
       setNeedsTextFixup();
     emitType01(Cond, kInstTypeDataRegShift, Lsl, SetFlags, Rn, Rd,
                encodeShiftRotateReg(Rm, OperandARM32::kNoShift, Rs), NoChecks);
     return;
   }
   }
 }
 
 void AssemblerARM32::mov(const Operand *OpRd, const Operand *OpSrc,
                          CondARM32::Cond Cond) {
   // MOV (register) - ARM section A8.8.104, encoding A1:
   //   mov{S}<c> <Rd>, <Rn>
   //
   // cccc0001101s0000dddd00000000mmmm where cccc=Cond, s=SetFlags, dddd=Rd,
   // and nnnn=Rn.
   //
   // MOV (immediate) - ARM section A8.8.102, encoding A1:
   //   mov{S}<c> <Rd>, #<RotatedImm8>
   //
   // cccc0011101s0000ddddiiiiiiiiiiii where cccc=Cond, s=SetFlags, dddd=Rd,
   // and iiiiiiiiiiii=RotatedImm8=Src.  Note: We don't use movs in this
   // assembler.
   IValueT Rd;
-  if (decodeOperand(OpRd, Rd) != DecodedAsRegister)
+  if (encodeOperand(OpRd, Rd) != EncodedAsRegister)
     return setNeedsTextFixup();
   constexpr bool SetFlags = false;
   constexpr IValueT Rn = 0;
   constexpr IValueT Mov = B3 | B2 | B0; // 1101.
   emitType01(Mov, Rd, Rn, OpSrc, SetFlags, Cond, RdIsPcAndSetFlags);
 }
 
 void AssemblerARM32::emitMovw(IValueT Opcode, IValueT Rd, IValueT Imm16,
                               bool SetFlags, CondARM32::Cond Cond) {
   if (!isConditionDefined(Cond) || !Utils::IsAbsoluteUint(16, Imm16))
     return setNeedsTextFixup();
   AssemblerBuffer::EnsureCapacity ensured(&Buffer);
   const IValueT Encoding = encodeCondition(Cond) << kConditionShift | Opcode |
                            (encodeBool(SetFlags) << kSShift) |
                            ((Imm16 >> 12) << 16) | Rd << kRdShift |
                            (Imm16 & 0xfff);
   emitInst(Encoding);
 }
 
 void AssemblerARM32::movw(const Operand *OpRd, const Operand *OpSrc,
                           CondARM32::Cond Cond) {
   IValueT Rd;
-  if (decodeOperand(OpRd, Rd) != DecodedAsRegister)
+  if (encodeOperand(OpRd, Rd) != EncodedAsRegister)
     return setNeedsTextFixup();
   if (const auto *Src = llvm::dyn_cast<ConstantRelocatable>(OpSrc)) {
     // MOVW (immediate) - ARM section A8.8.102, encoding A2:
     //  movw<c> <Rd>, #<imm16>
     //
     // cccc00110000iiiiddddiiiiiiiiiiii where cccc=Cond, dddd=Rd, and
     // iiiiiiiiiiiiiiii=imm16.
     if (!isConditionDefined(Cond))
       // Conditions of rule violated.
       return setNeedsTextFixup();
     // Use 0 for the lower 16 bits of the relocatable, and add a fixup to
     // install the correct bits.
     constexpr bool IsMovW = true;
     emitFixup(createMoveFixup(IsMovW, Src));
     constexpr IValueT Imm16 = 0;
     constexpr bool SetFlags = false;
     emitMovw(B25 | B24, Rd, Imm16, SetFlags, Cond);
     return;
   }
   IValueT ConstVal;
-  if (decodeOperand(OpSrc, ConstVal) != DecodedAsConstI32)
+  if (encodeOperand(OpSrc, ConstVal) != EncodedAsConstI32)
     return setNeedsTextFixup();
   // TODO(kschimpf): Determine if we want to handle rotated immediate 8 values
   // to handle cases where the constant is greater than 16 bits (encoding A1
   // below).  For now, handle using encoding A2.
   constexpr bool SetFlags = 0;
   emitMovw(B25 | B24, Rd, ConstVal, SetFlags, Cond);
   return;
 
   // MOVW (immediate) - ARM section A8.8.102, encoding A1:
   //   movw<c> <Rd>, #<RotatedImm8>
   //
   // cccc0011101s0000ddddiiiiiiiiiiii where cccc=Cond, dddd=Rd, s=SetFlags=0,
   // and iiiiiiiiiiii is a shift-rotated value defining RotatedImm8.
 }
 
 void AssemblerARM32::movt(const Operand *OpRd, const Operand *OpSrc,
                           CondARM32::Cond Cond) {
   IValueT Rd;
-  if (decodeOperand(OpRd, Rd) != DecodedAsRegister)
+  if (encodeOperand(OpRd, Rd) != EncodedAsRegister)
     return setNeedsTextFixup();
   auto *Src = llvm::dyn_cast<ConstantRelocatable>(OpSrc);
   if (Src == nullptr)
     return setNeedsTextFixup();
   // MOVT - ARM section A8.8.102, encoding A2:
   //  movt<c> <Rd>, #<imm16>
   //
   // cccc00110100iiiiddddiiiiiiiiiiii where cccc=Cond, dddd=Rd, and
   // iiiiiiiiiiiiiiii=imm16.
   if (!isConditionDefined(Cond))
@@ skipping 18 matching lines @@
   //
   // cccc0011111s0000ddddiiiiiiiiiiii where cccc=Cond, s=SetFlags=0, dddd=Rd,
   // and iiiiiiiiiiii=const
   //
   // MVN (register) - ARM section A8.8.116, encoding A1:
   //   mvn{s}<c> <Rd>, <Rm>{, <shift>
   //
   // cccc0001111s0000ddddiiiiitt0mmmm where cccc=Cond, s=SetFlags=0, dddd=Rd,
   // mmmm=Rm, iiii defines shift constant, and tt=ShiftKind.
   IValueT Rd;
-  if (decodeOperand(OpRd, Rd) != DecodedAsRegister)
+  if (encodeOperand(OpRd, Rd) != EncodedAsRegister)
     return setNeedsTextFixup();
   constexpr IValueT MvnOpcode = B3 | B2 | B1 | B0; // i.e. 1111
   constexpr IValueT Rn = 0;
   constexpr bool SetFlags = false;
   emitType01(MvnOpcode, Rd, Rn, OpSrc, SetFlags, Cond, RdIsPcAndSetFlags);
 }
 
 void AssemblerARM32::sbc(const Operand *OpRd, const Operand *OpRn,
                          const Operand *OpSrc1, bool SetFlags,
                          CondARM32::Cond Cond) {
@@ skipping 13 matching lines @@
 }
 
 void AssemblerARM32::sdiv(const Operand *OpRd, const Operand *OpRn,
                           const Operand *OpSrc1, CondARM32::Cond Cond) {
   // SDIV - ARM section A8.8.165, encoding A1.
   //   sdiv<c> <Rd>, <Rn>, <Rm>
   //
   // cccc01110001dddd1111mmmm0001nnnn where cccc=Cond, dddd=Rd, nnnn=Rn, and
   // mmmm=Rm.
   IValueT Rd;
-  if (decodeOperand(OpRd, Rd) != DecodedAsRegister)
+  if (encodeOperand(OpRd, Rd) != EncodedAsRegister)
     return setNeedsTextFixup();
   IValueT Rn;
-  if (decodeOperand(OpRn, Rn) != DecodedAsRegister)
+  if (encodeOperand(OpRn, Rn) != EncodedAsRegister)
     return setNeedsTextFixup();
   IValueT Rm;
-  if (decodeOperand(OpSrc1, Rm) != DecodedAsRegister)
+  if (encodeOperand(OpSrc1, Rm) != EncodedAsRegister)
     return setNeedsTextFixup();
   if (Rd == RegARM32::Encoded_Reg_pc || Rn == RegARM32::Encoded_Reg_pc ||
       Rm == RegARM32::Encoded_Reg_pc)
     llvm::report_fatal_error("Sdiv instruction unpredictable on pc");
   // Assembler registers rd, rn, rm are encoded as rn, rm, rs.
   constexpr IValueT Opcode = 0;
   emitDivOp(Cond, Opcode, Rd, Rn, Rm);
 }
 
 void AssemblerARM32::str(const Operand *OpRt, const Operand *OpAddress,
                          CondARM32::Cond Cond, const TargetInfo &TInfo) {
   constexpr bool IsLoad = false;
   IValueT Rt;
-  if (decodeOperand(OpRt, Rt) != DecodedAsRegister)
+  if (encodeOperand(OpRt, Rt) != EncodedAsRegister)
     return setNeedsTextFixup();
   const Type Ty = OpRt->getType();
   switch (typeWidthInBytesLog2(Ty)) {
   case 3:
   // STRD is not implemented because target lowering handles i64 and double by
   // using two (32-bit) store instructions.  Note: Intenionally drop to
   // default case.
   default:
     llvm::report_fatal_error(std::string("Type ") + typeString(Ty) +
                              " not implementable using str\n");
@@ skipping 58 matching lines @@
   constexpr IValueT Orr = B3 | B2; // i.e. 1100
   emitType01(Orr, OpRd, OpRn, OpSrc1, SetFlags, Cond, RdIsPcAndSetFlags);
 }
 
 void AssemblerARM32::pop(const Operand *OpRt, CondARM32::Cond Cond) {
   // POP - ARM section A8.8.132, encoding A2:
   //   pop<c> {Rt}
   //
   // cccc010010011101dddd000000000100 where dddd=Rt and cccc=Cond.
   IValueT Rt;
-  if (decodeOperand(OpRt, Rt) != DecodedAsRegister)
+  if (encodeOperand(OpRt, Rt) != EncodedAsRegister)
     return setNeedsTextFixup();
   assert(Rt != RegARM32::Encoded_Reg_sp);
   // Same as load instruction.
   constexpr bool IsLoad = true;
   constexpr bool IsByte = false;
   IValueT Address = encodeImmRegOffset(RegARM32::Encoded_Reg_sp, kWordSize,
                                        OperandARM32Mem::PostIndex);
   emitMemOp(Cond, kInstTypeMemImmediate, IsLoad, IsByte, Rt, Address);
 }
 
 void AssemblerARM32::popList(const IValueT Registers, CondARM32::Cond Cond) {
   // POP - ARM section A8.*.131, encoding A1:
   //   pop<c> <registers>
   //
   // cccc100010111101rrrrrrrrrrrrrrrr where cccc=Cond and
   // rrrrrrrrrrrrrrrr=Registers (one bit for each GP register).
   constexpr bool IsLoad = true;
   emitMultiMemOp(Cond, IA_W, IsLoad, RegARM32::Encoded_Reg_sp, Registers);
 }
 
 void AssemblerARM32::push(const Operand *OpRt, CondARM32::Cond Cond) {
   // PUSH - ARM section A8.8.133, encoding A2:
   //   push<c> {Rt}
   //
   // cccc010100101101dddd000000000100 where dddd=Rt and cccc=Cond.
   IValueT Rt;
-  if (decodeOperand(OpRt, Rt) != DecodedAsRegister)
+  if (encodeOperand(OpRt, Rt) != EncodedAsRegister)
     return setNeedsTextFixup();
   assert(Rt != RegARM32::Encoded_Reg_sp);
   // Same as store instruction.
   constexpr bool isLoad = false;
   constexpr bool isByte = false;
   IValueT Address = encodeImmRegOffset(RegARM32::Encoded_Reg_sp, -kWordSize,
                                        OperandARM32Mem::PreIndex);
   emitMemOp(Cond, kInstTypeMemImmediate, isLoad, isByte, Rt, Address);
 }
 
 void AssemblerARM32::pushList(const IValueT Registers, CondARM32::Cond Cond) {
   // PUSH - ARM section A8.8.133, encoding A1:
   //   push<c> <Registers>
   //
   // cccc100100101101rrrrrrrrrrrrrrrr where cccc=Cond and
   // rrrrrrrrrrrrrrrr=Registers (one bit for each GP register).
   constexpr bool IsLoad = false;
   emitMultiMemOp(Cond, DB_W, IsLoad, RegARM32::Encoded_Reg_sp, Registers);
 }
 
 void AssemblerARM32::mla(const Operand *OpRd, const Operand *OpRn,
                          const Operand *OpRm, const Operand *OpRa,
                          CondARM32::Cond Cond) {
   IValueT Rd;
-  if (decodeOperand(OpRd, Rd) != DecodedAsRegister)
+  if (encodeOperand(OpRd, Rd) != EncodedAsRegister)
     return setNeedsTextFixup();
   IValueT Rn;
-  if (decodeOperand(OpRn, Rn) != DecodedAsRegister)
+  if (encodeOperand(OpRn, Rn) != EncodedAsRegister)
     return setNeedsTextFixup();
   IValueT Rm;
-  if (decodeOperand(OpRm, Rm) != DecodedAsRegister)
+  if (encodeOperand(OpRm, Rm) != EncodedAsRegister)
     return setNeedsTextFixup();
   IValueT Ra;
-  if (decodeOperand(OpRa, Ra) != DecodedAsRegister)
+  if (encodeOperand(OpRa, Ra) != EncodedAsRegister)
     return setNeedsTextFixup();
   // MLA - ARM section A8.8.114, encoding A1.
   //   mla{s}<c> <Rd>, <Rn>, <Rm>, <Ra>
   //
   // cccc0000001sddddaaaammmm1001nnnn where cccc=Cond, s=SetFlags, dddd=Rd,
   // aaaa=Ra, mmmm=Rm, and nnnn=Rn.
   if (Rd == RegARM32::Encoded_Reg_pc || Rn == RegARM32::Encoded_Reg_pc ||
       Rm == RegARM32::Encoded_Reg_pc || Ra == RegARM32::Encoded_Reg_pc)
     llvm::report_fatal_error("Mul instruction unpredictable on pc");
   constexpr IValueT MlaOpcode = B21;
   constexpr bool SetFlags = false;
   // Assembler registers rd, rn, rm, ra are encoded as rn, rm, rs, rd.
   emitMulOp(Cond, MlaOpcode, Ra, Rd, Rn, Rm, SetFlags);
 }
 
 void AssemblerARM32::mul(const Operand *OpRd, const Operand *OpRn,
                          const Operand *OpSrc1, bool SetFlags,
                          CondARM32::Cond Cond) {
   IValueT Rd;
-  if (decodeOperand(OpRd, Rd) != DecodedAsRegister)
+  if (encodeOperand(OpRd, Rd) != EncodedAsRegister)
     return setNeedsTextFixup();
   IValueT Rn;
-  if (decodeOperand(OpRn, Rn) != DecodedAsRegister)
+  if (encodeOperand(OpRn, Rn) != EncodedAsRegister)
     return setNeedsTextFixup();
   IValueT Rm;
-  if (decodeOperand(OpSrc1, Rm) != DecodedAsRegister)
+  if (encodeOperand(OpSrc1, Rm) != EncodedAsRegister)
     return setNeedsTextFixup();
   // MUL - ARM section A8.8.114, encoding A1.
   //   mul{s}<c> <Rd>, <Rn>, <Rm>
   //
   // cccc0000000sdddd0000mmmm1001nnnn where cccc=Cond, dddd=Rd, nnnn=Rn,
   // mmmm=Rm, and s=SetFlags.
   if (Rd == RegARM32::Encoded_Reg_pc || Rn == RegARM32::Encoded_Reg_pc ||
       Rm == RegARM32::Encoded_Reg_pc)
     llvm::report_fatal_error("Mul instruction unpredictable on pc");
   // Assembler registers rd, rn, rm are encoded as rn, rm, rs.
   constexpr IValueT MulOpcode = 0;
   emitMulOp(Cond, MulOpcode, RegARM32::Encoded_Reg_r0, Rd, Rn, Rm, SetFlags);
 }
 
 void AssemblerARM32::udiv(const Operand *OpRd, const Operand *OpRn,
                           const Operand *OpSrc1, CondARM32::Cond Cond) {
   // UDIV - ARM section A8.8.248, encoding A1.
   //   udiv<c> <Rd>, <Rn>, <Rm>
   //
   // cccc01110011dddd1111mmmm0001nnnn where cccc=Cond, dddd=Rd, nnnn=Rn, and
   // mmmm=Rm.
   IValueT Rd;
-  if (decodeOperand(OpRd, Rd) != DecodedAsRegister)
+  if (encodeOperand(OpRd, Rd) != EncodedAsRegister)
     return setNeedsTextFixup();
   IValueT Rn;
-  if (decodeOperand(OpRn, Rn) != DecodedAsRegister)
+  if (encodeOperand(OpRn, Rn) != EncodedAsRegister)
     return setNeedsTextFixup();
   IValueT Rm;
-  if (decodeOperand(OpSrc1, Rm) != DecodedAsRegister)
+  if (encodeOperand(OpSrc1, Rm) != EncodedAsRegister)
     return setNeedsTextFixup();
   if (Rd == RegARM32::Encoded_Reg_pc || Rn == RegARM32::Encoded_Reg_pc ||
       Rm == RegARM32::Encoded_Reg_pc)
     llvm::report_fatal_error("Udiv instruction unpredictable on pc");
   // Assembler registers rd, rn, rm are encoded as rn, rm, rs.
   constexpr IValueT Opcode = B21;
   emitDivOp(Cond, Opcode, Rd, Rn, Rm);
 }
 
 void AssemblerARM32::sub(const Operand *OpRd, const Operand *OpRn,
@@ skipping 40 matching lines @@
                            CondARM32::Cond Cond) {
   // UMULL - ARM section A8.8.257, encoding A1:
   //   umull<c> <RdLo>, <RdHi>, <Rn>, <Rm>
   //
   // cccc0000100shhhhllllmmmm1001nnnn where hhhh=RdHi, llll=RdLo, nnnn=Rn,
   // mmmm=Rm, and s=SetFlags
   IValueT RdLo;
   IValueT RdHi;
   IValueT Rn;
   IValueT Rm;
-  if (decodeOperand(OpRdLo, RdLo) != DecodedAsRegister ||
-      decodeOperand(OpRdHi, RdHi) != DecodedAsRegister ||
-      decodeOperand(OpRn, Rn) != DecodedAsRegister ||
-      decodeOperand(OpRm, Rm) != DecodedAsRegister)
+  if (encodeOperand(OpRdLo, RdLo) != EncodedAsRegister ||
+      encodeOperand(OpRdHi, RdHi) != EncodedAsRegister ||
+      encodeOperand(OpRn, Rn) != EncodedAsRegister ||
+      encodeOperand(OpRm, Rm) != EncodedAsRegister)
     return setNeedsTextFixup();
   if (RdHi == RegARM32::Encoded_Reg_pc || RdLo == RegARM32::Encoded_Reg_pc ||
       Rn == RegARM32::Encoded_Reg_pc || Rm == RegARM32::Encoded_Reg_pc ||
       RdHi == RdLo)
     llvm::report_fatal_error("Umull instruction unpredictable on pc");
   constexpr bool SetFlags = false;
   emitMulOp(Cond, B23, RdLo, RdHi, Rn, Rm, SetFlags);
 }
 
 void AssemblerARM32::uxt(const Operand *OpRd, const Operand *OpSrc0,
                          CondARM32::Cond Cond) {
   IValueT Rd;
-  if (decodeOperand(OpRd, Rd) != DecodedAsRegister)
+  if (encodeOperand(OpRd, Rd) != EncodedAsRegister)
     return setNeedsTextFixup();
   // Note: For the moment, we assume no rotation is specified.
   RotationValue Rotation = kRotateNone;
   constexpr IValueT Rn = RegARM32::Encoded_Reg_pc;
   IValueT Rm;
-  if (decodeOperand(OpSrc0, Rm) != DecodedAsRegister)
+  if (encodeOperand(OpSrc0, Rm) != EncodedAsRegister)
     return setNeedsTextFixup();
   switch (typeWidthInBytes(OpSrc0->getType())) {
   default:
     return setNeedsTextFixup();
   case 1: {
     // UXTB - ARM section A8.8.274, encoding A1:
     //   uxtb<c> <Rd>, <Rm>{, <rotate>}
     //
     // cccc011011101111ddddrr000111mmmm where cccc=Cond, dddd=Rd, mmmm=Rm, and
     // rr defined (RotationValue) rotate.
     constexpr IValueT Opcode = B26 | B25 | B23 | B22 | B21;
     emitUxt(Cond, Opcode, Rd, Rn, Rm, Rotation);
     return;
   }
   case 2: {
     // UXTH - ARM section A8.8.276, encoding A1:
     //   uxth<c> <Rd>< <Rm>{, <rotate>}
     //
     // cccc01101111nnnnddddrr000111mmmm where cccc=Cond, dddd=Rd, mmmm=Rm, and
     // rr defined (RotationValue) rotate.
     constexpr IValueT Opcode = B26 | B25 | B23 | B22 | B21 | B20;
     emitUxt(Cond, Opcode, Rd, Rn, Rm, Rotation);
     return;
   }
   }
 }
 
 } // end of namespace ARM32
 } // end of namespace Ice