More coverage of load/stores in ARM integrated assembler.

src/IceAssemblerARM32.h

 //===- subzero/src/IceAssemblerARM32.h - Assembler for ARM32 ----*- C++ -*-===//
 //
 // Copyright (c) 2013, the Dart project authors.  Please see the AUTHORS file
 // for details. All rights reserved. Use of this source code is governed by a
 // BSD-style license that can be found in the LICENSE file.
 //
 // Modified by the Subzero authors.
 //
 //===----------------------------------------------------------------------===//
 //
@@ skipping 319 matching lines @@
                   EmitChecks RuleChecks);
 
   // Same as above, but the value for Rd and Rn have already been converted
   // into instruction values.
   void emitType01(IValueT Opcode, IValueT OpRd, IValueT OpRn,
                   const Operand *OpSrc1, bool SetFlags, CondARM32::Cond Cond,
                   EmitChecks RuleChecks);
 
   void emitType05(CondARM32::Cond COnd, int32_t Offset, bool Link);
 
-  // Pattern ccccoooaabalnnnnttttaaaaaaaaaaaa where cccc=Cond, ooo=InstType,
-  // l=isLoad, b=isByte, and aaa0a0aaaa0000aaaaaaaaaaaa=Address. Note that
-  // Address is assumed to be defined by decodeAddress() in
-  // IceAssemblerARM32.cpp.
+  // Emit ccccoooaabalnnnnttttaaaaaaaaaaaa where cccc=Cond,
+  // ooo=InstType, l=isLoad, b=isByte, and
+  // aaa0a0aaaa0000aaaaaaaaaaaa=Address. Note that Address is assumed to be
+  // defined by decodeAddress() in IceAssemblerARM32.cpp.
   void emitMemOp(CondARM32::Cond Cond, IValueT InstType, bool IsLoad,
-                 bool IsByte, uint32_t Rt, uint32_t Address);
+                 bool IsByte, IValueT Rt, IValueT Address);
+
+  // Emit ldr/ldrb/str/strb instruction with given address.
+  void emitMemOp(CondARM32::Cond Cond, bool IsLoad, bool IsByte, IValueT Rt,
+                 const Operand *OpAddress, const TargetInfo &TInfo);
+
+  // Emit ldrh/ldrd/strh/strd instruction with given address using encoding 3.
+  void emitMemOpEnc3(CondARM32::Cond Cond, IValueT Opcode, IValueT Rt,
+                     const Operand *OpAddress, const TargetInfo &TInfo);
 
   // Pattern cccc100aaaalnnnnrrrrrrrrrrrrrrrr where cccc=Cond,
   // aaaa<<21=AddressMode, l=IsLoad, nnnn=BaseReg, and
   // rrrrrrrrrrrrrrrr is bitset of Registers.
   void emitMultiMemOp(CondARM32::Cond Cond, BlockAddressMode AddressMode,
                       bool IsLoad, IValueT BaseReg, IValueT Registers);
 
   // Pattern cccc011100x1dddd1111mmmm0001nnn where cccc=Cond,
   // x=Opcode, dddd=Rd, nnnn=Rn, mmmm=Rm.
   void emitDivOp(CondARM32::Cond Cond, IValueT Opcode, IValueT Rd, IValueT Rn,
@@ skipping 28 matching lines @@
   // cccc=Cond, xxxxxxx<<21=Opcode, dddd=Rd, s=SetFlags, and
   // iiiiiiiiiiiiiiii=Imm16.
   void emitMovw(IValueT Opcode, IValueT Rd, IValueT Imm16, bool SetFlags,
                 CondARM32::Cond Cond);
 };
 
 } // end of namespace ARM32
 } // end of namespace Ice
 
 #endif // SUBZERO_SRC_ICEASSEMBLERARM32_H