More coverage of load/stores in ARM integrated assembler.

src/DartARM32/assembler_arm.cc

 // Copyright (c) 2013, the Dart project authors.  Please see the AUTHORS file
 // for details. All rights reserved. Use of this source code is governed by a
 // BSD-style license that can be found in the LICENSE file.
 //
 // This is forked from Dart revision df52deea9f25690eb8b66c5995da92b70f7ac1fe
 // Please update the (git) revision if we merge changes from Dart.
 // https://code.google.com/p/dart/wiki/GettingTheSource
 
 #include "vm/globals.h"  // NOLINT
 #if defined(TARGET_ARCH_ARM)
@@ skipping 10 matching lines @@
 #if !defined(USING_SIMULATOR) && !defined(__linux__) && !defined(ANDROID)
 #error ARM cross-compile only supported on Linux
 #endif
 
 namespace dart {
 
 DECLARE_FLAG(bool, allow_absolute_addresses);
 DEFINE_FLAG(bool, print_stop_message, true, "Print stop message.");
 DECLARE_FLAG(bool, inline_alloc);
 
+#if 0
+// Moved to encodeImmRegOffsetEnc3 in IceAssemblerARM32.cpp
 uint32_t Address::encoding3() const {
   if (kind_ == Immediate) {
     uint32_t offset = encoding_ & kOffset12Mask;
     ASSERT(offset < 256);
     return (encoding_ & ~kOffset12Mask) | B22 |
            ((offset & 0xf0) << 4) | (offset & 0xf);
   }
   ASSERT(kind_ == IndexRegister);
   return encoding_;
 }
-
+#endif
 
 uint32_t Address::vencoding() const {
   ASSERT(kind_ == Immediate);
   uint32_t offset = encoding_ & kOffset12Mask;
   ASSERT(offset < (1 << 10));  // In the range 0 to +1020.
   ASSERT(Utils::IsAligned(offset, 4));  // Multiple of 4.
   int mode = encoding_ & ((8|4|1) << 21);
   ASSERT((mode == Offset) || (mode == NegOffset));
   uint32_t vencoding = (encoding_ & (0xf << kRnShift)) | (offset >> 2);
   if (mode == Offset) {
@@ skipping 58 matching lines @@
   ASSERT(rd != kNoRegister);
   ASSERT(cond != kNoCondition);
   int32_t encoding = (static_cast<int32_t>(cond) << kConditionShift) |
                      B26 | (ad.kind() == Address::Immediate ? 0 : B25) |
                      (load ? L : 0) |
                      (byte ? B : 0) |
                      (static_cast<int32_t>(rd) << kRdShift) |
                      ad.encoding();
   Emit(encoding);
 }
-#endif
 
+// Moved to AssemblerARM32::emitMemOpEnc3();
 void Assembler::EmitMemOpAddressMode3(Condition cond,
                                       int32_t mode,
                                       Register rd,
                                       Address ad) {
   ASSERT(rd != kNoRegister);
   ASSERT(cond != kNoCondition);
   int32_t encoding = (static_cast<int32_t>(cond) << kConditionShift) |
                      mode |
                      (static_cast<int32_t>(rd) << kRdShift) |
                      ad.encoding3();
   Emit(encoding);
 }
 
-#if 0
 // Moved to ARM32::AssemblerARM32::emitMuliMemOp()
 void Assembler::EmitMultiMemOp(Condition cond,
                                BlockAddressMode am,
                                bool load,
                                Register base,
                                RegList regs) {
   ASSERT(base != kNoRegister);
   ASSERT(cond != kNoCondition);
   int32_t encoding = (static_cast<int32_t>(cond) << kConditionShift) |
                      B27 |
@@ skipping 38 matching lines @@
                      static_cast<int32_t>(rm);
   Emit(encoding);
 }
 
 
 #if 0
 // Moved to ARM32::AssemblerARM32::and_()
 void Assembler::and_(Register rd, Register rn, Operand o, Condition cond) {
   EmitType01(cond, o.type(), AND, 0, rn, rd, o);
 }
-#endif
 
-#if 0
 // Moved to ARM32::AssemberARM32::eor()
 void Assembler::eor(Register rd, Register rn, Operand o, Condition cond) {
   EmitType01(cond, o.type(), EOR, 0, rn, rd, o);
 }
 
 // Moved to ARM32::AssemberARM32::sub()
 void Assembler::sub(Register rd, Register rn, Operand o, Condition cond) {
   EmitType01(cond, o.type(), SUB, 0, rn, rd, o);
 }
 #endif
 
 void Assembler::rsb(Register rd, Register rn, Operand o, Condition cond) {
   EmitType01(cond, o.type(), RSB, 0, rn, rd, o);
 }
 
 void Assembler::rsbs(Register rd, Register rn, Operand o, Condition cond) {
   EmitType01(cond, o.type(), RSB, 1, rn, rd, o);
 }
 
-
 #if 0
 // Moved to ARM32::AssemberARM32::add()
 void Assembler::add(Register rd, Register rn, Operand o, Condition cond) {
   EmitType01(cond, o.type(), ADD, 0, rn, rd, o);
 }
 
 // Moved to ARM32::AssemberARM32::add()
 void Assembler::adds(Register rd, Register rn, Operand o, Condition cond) {
   EmitType01(cond, o.type(), ADD, 1, rn, rd, o);
 }
 
 // Moved to ARM32::AssemberARM32::sub()
 void Assembler::subs(Register rd, Register rn, Operand o, Condition cond) {
   EmitType01(cond, o.type(), SUB, 1, rn, rd, o);
 }
 
 // Moved to ARM32::AssemberARM32::adc()
 void Assembler::adc(Register rd, Register rn, Operand o, Condition cond) {
   EmitType01(cond, o.type(), ADC, 0, rn, rd, o);
 }
 
 // Moved to ARM32::AssemberARM32::adc()
 void Assembler::adcs(Register rd, Register rn, Operand o, Condition cond) {
   EmitType01(cond, o.type(), ADC, 1, rn, rd, o);
 }
 #endif
 
-
 void Assembler::sbc(Register rd, Register rn, Operand o, Condition cond) {
   EmitType01(cond, o.type(), SBC, 0, rn, rd, o);
 }
 
 
 void Assembler::sbcs(Register rd, Register rn, Operand o, Condition cond) {
   EmitType01(cond, o.type(), SBC, 1, rn, rd, o);
 }
 
 
 void Assembler::rsc(Register rd, Register rn, Operand o, Condition cond) {
   EmitType01(cond, o.type(), RSC, 0, rn, rd, o);
 }
 
 #if 0
 // Moved to ARM32::AssemblerARM32::tst()
 void Assembler::tst(Register rn, Operand o, Condition cond) {
   EmitType01(cond, o.type(), TST, 1, rn, R0, o);
 }
 #endif
 
 void Assembler::teq(Register rn, Operand o, Condition cond) {
   EmitType01(cond, o.type(), TEQ, 1, rn, R0, o);
 }
 
-
 #if 0
 // Moved to ARM32::AssemblerARM32::cmp()
 void Assembler::cmp(Register rn, Operand o, Condition cond) {
   EmitType01(cond, o.type(), CMP, 1, rn, R0, o);
 }
 #endif
 
 
 void Assembler::cmn(Register rn, Operand o, Condition cond) {
   EmitType01(cond, o.type(), CMN, 1, rn, R0, o);
@@ skipping 51 matching lines @@
   ASSERT(rd != PC);
   ASSERT(rm != PC);
   int32_t encoding = (static_cast<int32_t>(cond) << kConditionShift) |
                      B24 | B22 | B21 | (0xf << 16) |
                      (static_cast<int32_t>(rd) << kRdShift) |
                      (0xf << 8) | B4 | static_cast<int32_t>(rm);
   Emit(encoding);
 }
 
 
-#if
+#if 0
 // Moved to ARM32::AssemblerARM32::movw()
 void Assembler::movw(Register rd, uint16_t imm16, Condition cond) {
   ASSERT(cond != kNoCondition);
   int32_t encoding = static_cast<int32_t>(cond) << kConditionShift |
                      B25 | B24 | ((imm16 >> 12) << 16) |
                      static_cast<int32_t>(rd) << kRdShift | (imm16 & 0xfff);
   Emit(encoding);
 }
 
 
 // Moved to ARM32::AssemblerARM32::movt()
 void Assembler::movt(Register rd, uint16_t imm16, Condition cond) {
   ASSERT(cond != kNoCondition);
   int32_t encoding = static_cast<int32_t>(cond) << kConditionShift |
                      B25 | B24 | B22 | ((imm16 >> 12) << 16) |
                      static_cast<int32_t>(rd) << kRdShift | (imm16 & 0xfff);
   Emit(encoding);
 }
-#endif
 
-#if 0
 // Moved to ARM32::AssemblerARM32::emitMulOp()
 void Assembler::EmitMulOp(Condition cond, int32_t opcode,
                           Register rd, Register rn,
                           Register rm, Register rs) {
   ASSERT(rd != kNoRegister);
   ASSERT(rn != kNoRegister);
   ASSERT(rm != kNoRegister);
   ASSERT(rs != kNoRegister);
   ASSERT(cond != kNoCondition);
   int32_t encoding = opcode |
@@ skipping 2230 matching lines @@
   ASSERT(shift_imm.encoding() != 0);  // Do not use Lsl if no shift is wanted.
   mov(rd, Operand(rm, LSL, shift_imm.encoding()), cond);
 }
 
 // Moved to ARM32::AssemblerARM32::lsl()
 void Assembler::Lsl(Register rd, Register rm, Register rs, Condition cond) {
   mov(rd, Operand(rm, LSL, rs), cond);
 }
 #endif
 
-
 void Assembler::Lsr(Register rd, Register rm, const Operand& shift_imm,
                     Condition cond) {
   ASSERT(shift_imm.type() == 1);
   uint32_t shift = shift_imm.encoding();
   ASSERT(shift != 0);  // Do not use Lsr if no shift is wanted.
   if (shift == 32) {
     shift = 0;  // Comply to UAL syntax.
   }
   mov(rd, Operand(rm, LSR, shift), cond);
 }
@@ skipping 1068 matching lines @@
 
 
 const char* Assembler::FpuRegisterName(FpuRegister reg) {
   ASSERT((0 <= reg) && (reg < kNumberOfFpuRegisters));
   return fpu_reg_names[reg];
 }
 
 }  // namespace dart
 
 #endif  // defined TARGET_ARCH_ARM