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Side by Side Diff: runtime/vm/assembler_mips_test.cc

Issue 14854010: On MIPS, keeps Object::null() in a register. (Closed) Base URL: http://dart.googlecode.com/svn/branches/bleeding_edge/dart/
Patch Set: Created 7 years, 7 months ago
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1 // Copyright (c) 2013, the Dart project authors. Please see the AUTHORS file 1 // Copyright (c) 2013, the Dart project authors. Please see the AUTHORS file
2 // for details. All rights reserved. Use of this source code is governed by a 2 // for details. All rights reserved. Use of this source code is governed by a
3 // BSD-style license that can be found in the LICENSE file. 3 // BSD-style license that can be found in the LICENSE file.
4 4
5 #include "vm/globals.h" 5 #include "vm/globals.h"
6 #if defined(TARGET_ARCH_MIPS) 6 #if defined(TARGET_ARCH_MIPS)
7 7
8 #include "vm/assembler.h" 8 #include "vm/assembler.h"
9 #include "vm/os.h" 9 #include "vm/os.h"
10 #include "vm/unit_test.h" 10 #include "vm/unit_test.h"
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1053 typedef int (*SimpleCode)(); 1053 typedef int (*SimpleCode)();
1054 EXPECT_EQ(42, EXECUTE_TEST_CODE_INT32(SimpleCode, test->entry())); 1054 EXPECT_EQ(42, EXECUTE_TEST_CODE_INT32(SimpleCode, test->entry()));
1055 } 1055 }
1056 1056
1057 1057
1058 ASSEMBLER_TEST_GENERATE(AddOverflow_detect, assembler) { 1058 ASSEMBLER_TEST_GENERATE(AddOverflow_detect, assembler) {
1059 Register left = T0; 1059 Register left = T0;
1060 Register right = T1; 1060 Register right = T1;
1061 Register result = T2; 1061 Register result = T2;
1062 Register overflow = T3; 1062 Register overflow = T3;
1063 Register scratch = T4;
1063 Label error, done; 1064 Label error, done;
1064 1065
1065 __ LoadImmediate(V0, 1); // Success value. 1066 __ LoadImmediate(V0, 1); // Success value.
1066 1067
1067 __ LoadImmediate(left, 0x7fffffff); 1068 __ LoadImmediate(left, 0x7fffffff);
1068 __ LoadImmediate(right, 1); 1069 __ LoadImmediate(right, 1);
1069 __ AdduDetectOverflow(result, left, right, overflow); 1070 __ AdduDetectOverflow(result, left, right, overflow);
1070 __ bgez(overflow, &error); // INT_MAX + 1 overflows. 1071 __ bgez(overflow, &error); // INT_MAX + 1 overflows.
1071 1072
1072 __ LoadImmediate(left, 0x7fffffff); 1073 __ LoadImmediate(left, 0x7fffffff);
(...skipping 14 matching lines...) Expand all
1087 __ LoadImmediate(right, 654321); 1088 __ LoadImmediate(right, 654321);
1088 __ AdduDetectOverflow(result, left, right, overflow); 1089 __ AdduDetectOverflow(result, left, right, overflow);
1089 __ bltz(overflow, &error); // 123456 + 654321 does not overflow. 1090 __ bltz(overflow, &error); // 123456 + 654321 does not overflow.
1090 1091
1091 __ LoadImmediate(left, 0x80000000); 1092 __ LoadImmediate(left, 0x80000000);
1092 __ LoadImmediate(right, -1); 1093 __ LoadImmediate(right, -1);
1093 __ AdduDetectOverflow(result, left, right, overflow); 1094 __ AdduDetectOverflow(result, left, right, overflow);
1094 __ bgez(overflow, &error); // INT_MIN - 1 overflows. 1095 __ bgez(overflow, &error); // INT_MIN - 1 overflows.
1095 1096
1096 // result has 0x7fffffff. 1097 // result has 0x7fffffff.
1097 __ AdduDetectOverflow(result, result, result, overflow); 1098 __ AdduDetectOverflow(result, result, result, overflow, scratch);
1098 __ bgez(overflow, &error); // INT_MAX + INT_MAX overflows. 1099 __ bgez(overflow, &error); // INT_MAX + INT_MAX overflows.
1099 1100
1100 __ LoadImmediate(left, 0x80000000); 1101 __ LoadImmediate(left, 0x80000000);
1101 __ LoadImmediate(right, 0x80000000); 1102 __ LoadImmediate(right, 0x80000000);
1102 __ AdduDetectOverflow(result, left, right, overflow); 1103 __ AdduDetectOverflow(result, left, right, overflow);
1103 __ bgez(overflow, &error); // INT_MIN + INT_MIN overflows. 1104 __ bgez(overflow, &error); // INT_MIN + INT_MIN overflows.
1104 1105
1105 __ LoadImmediate(left, -123456); 1106 __ LoadImmediate(left, -123456);
1106 __ LoadImmediate(right, -654321); 1107 __ LoadImmediate(right, -654321);
1107 __ AdduDetectOverflow(result, left, right, overflow); 1108 __ AdduDetectOverflow(result, left, right, overflow);
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1343 A1); 1344 A1);
1344 __ lw(RA, Address(SP, 0 * kWordSize)); 1345 __ lw(RA, Address(SP, 0 * kWordSize));
1345 __ lw(CTX, Address(SP, 1 * kWordSize)); 1346 __ lw(CTX, Address(SP, 1 * kWordSize));
1346 __ addiu(SP, SP, Immediate(2 * kWordSize)); 1347 __ addiu(SP, SP, Immediate(2 * kWordSize));
1347 __ Ret(); 1348 __ Ret();
1348 } 1349 }
1349 1350
1350 } // namespace dart 1351 } // namespace dart
1351 1352
1352 #endif // defined TARGET_ARCH_MIPS 1353 #endif // defined TARGET_ARCH_MIPS
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