Chromium Code Reviews
chromiumcodereview-hr@appspot.gserviceaccount.com (chromiumcodereview-hr) | Please choose your nickname with Settings | Help | Chromium Project | Gerrit Changes | Sign out
(19)

Side by Side Diff: src/a64/cpu-a64.cc

Issue 148503002: A64: Synchronize with r15545. (Closed) Base URL: https://v8.googlecode.com/svn/branches/experimental/a64
Patch Set: Created 6 years, 11 months ago
Use n/p to move between diff chunks; N/P to move between comments. Draft comments are only viewable by you.
Jump to:
View unified diff | Download patch | Annotate | Revision Log
« no previous file with comments | « src/a64/codegen-a64.cc ('k') | src/a64/debug-a64.cc » ('j') | no next file with comments »
Toggle Intra-line Diffs ('i') | Expand Comments ('e') | Collapse Comments ('c') | Show Comments Hide Comments ('s')
OLDNEW
1 // Copyright 2013 the V8 project authors. All rights reserved. 1 // Copyright 2013 the V8 project authors. All rights reserved.
2 // Redistribution and use in source and binary forms, with or without 2 // Redistribution and use in source and binary forms, with or without
3 // modification, are permitted provided that the following conditions are 3 // modification, are permitted provided that the following conditions are
4 // met: 4 // met:
5 // 5 //
6 // * Redistributions of source code must retain the above copyright 6 // * Redistributions of source code must retain the above copyright
7 // notice, this list of conditions and the following disclaimer. 7 // notice, this list of conditions and the following disclaimer.
8 // * Redistributions in binary form must reproduce the above 8 // * Redistributions in binary form must reproduce the above
9 // copyright notice, this list of conditions and the following 9 // copyright notice, this list of conditions and the following
10 // disclaimer in the documentation and/or other materials provided 10 // disclaimer in the documentation and/or other materials provided
(...skipping 14 matching lines...) Expand all
25 // (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 25 // (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 // OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 26 // OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 27
28 // CPU specific code for arm independent of OS goes here. 28 // CPU specific code for arm independent of OS goes here.
29 #ifdef __arm__ 29 #ifdef __arm__
30 #include <sys/syscall.h> // For cache flushing. 30 #include <sys/syscall.h> // For cache flushing.
31 #endif 31 #endif
32 32
33 #include "v8.h" 33 #include "v8.h"
34 34
35 #if defined(V8_TARGET_ARCH_A64) 35 #if V8_TARGET_ARCH_A64
36 36
37 #include "a64/cpu-a64.h" 37 #include "a64/cpu-a64.h"
38 #include "a64/utils-a64.h" 38 #include "a64/utils-a64.h"
39 39
40 namespace v8 { 40 namespace v8 {
41 namespace internal { 41 namespace internal {
42 42
43 #ifdef DEBUG 43 #ifdef DEBUG
44 bool CpuFeatures::initialized_ = false; 44 bool CpuFeatures::initialized_ = false;
45 #endif 45 #endif
46 unsigned CpuFeatures::supported_ = 0; 46 unsigned CpuFeatures::supported_ = 0;
47 47
48 48
49 // Initialise to smallest possible cache size. 49 // Initialise to smallest possible cache size.
50 unsigned CpuFeatures::dcache_line_size_ = 1; 50 unsigned CpuFeatures::dcache_line_size_ = 1;
51 unsigned CpuFeatures::icache_line_size_ = 1; 51 unsigned CpuFeatures::icache_line_size_ = 1;
52 52
53 53
54 void CPU::SetUp() { 54 void CPU::SetUp() {
55 CpuFeatures::Probe(); 55 CpuFeatures::Probe();
56 } 56 }
57 57
58 58
59 bool CPU::SupportsCrankshaft() { 59 bool CPU::SupportsCrankshaft() {
60 return true; 60 return true;
61 } 61 }
62 62
63
63 void CPU::FlushICache(void* address, size_t length) { 64 void CPU::FlushICache(void* address, size_t length) {
64 if (length == 0) { 65 if (length == 0) {
65 return; 66 return;
66 } 67 }
67 68
68 #ifdef USE_SIMULATOR 69 #ifdef USE_SIMULATOR
69 // TODO(all): consider doing some cache simulation to ensure every address 70 // TODO(all): consider doing some cache simulation to ensure every address
70 // run has been synced. 71 // run has been synced.
71 USE(address); 72 USE(address);
72 USE(length); 73 USE(length);
(...skipping 127 matching lines...) Expand 10 before | Expand all | Expand 10 after
200 // Copy the content of the cache type register to a core register. 201 // Copy the content of the cache type register to a core register.
201 __asm__ __volatile__ ("mrs %[ctr], ctr_el0" // NOLINT 202 __asm__ __volatile__ ("mrs %[ctr], ctr_el0" // NOLINT
202 : [ctr] "=r" (cache_type_register)); 203 : [ctr] "=r" (cache_type_register));
203 return cache_type_register; 204 return cache_type_register;
204 #endif 205 #endif
205 } 206 }
206 207
207 } } // namespace v8::internal 208 } } // namespace v8::internal
208 209
209 #endif // V8_TARGET_ARCH_A64 210 #endif // V8_TARGET_ARCH_A64
OLDNEW
« no previous file with comments | « src/a64/codegen-a64.cc ('k') | src/a64/debug-a64.cc » ('j') | no next file with comments »

Powered by Google App Engine
This is Rietveld 408576698