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1 // Copyright 2013 the V8 project authors. All rights reserved. | 1 // Copyright 2013 the V8 project authors. All rights reserved. |
2 // | 2 // |
3 // Redistribution and use in source and binary forms, with or without | 3 // Redistribution and use in source and binary forms, with or without |
4 // modification, are permitted provided that the following conditions are | 4 // modification, are permitted provided that the following conditions are |
5 // met: | 5 // met: |
6 // | 6 // |
7 // * Redistributions of source code must retain the above copyright | 7 // * Redistributions of source code must retain the above copyright |
8 // notice, this list of conditions and the following disclaimer. | 8 // notice, this list of conditions and the following disclaimer. |
9 // * Redistributions in binary form must reproduce the above | 9 // * Redistributions in binary form must reproduce the above |
10 // copyright notice, this list of conditions and the following | 10 // copyright notice, this list of conditions and the following |
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21 // OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, | 21 // OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, |
22 // SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT | 22 // SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT |
23 // LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, | 23 // LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, |
24 // DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY | 24 // DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY |
25 // THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT | 25 // THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
26 // (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE | 26 // (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE |
27 // OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. | 27 // OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
28 | 28 |
29 #include "v8.h" | 29 #include "v8.h" |
30 | 30 |
31 #if defined(V8_TARGET_ARCH_A64) | 31 #if V8_TARGET_ARCH_A64 |
32 | 32 |
33 #include "a64/assembler-a64-inl.h" | 33 #include "a64/assembler-a64-inl.h" |
34 | 34 |
35 namespace v8 { | 35 namespace v8 { |
36 namespace internal { | 36 namespace internal { |
37 | 37 |
38 | 38 |
39 // ----------------------------------------------------------------------------- | 39 // ----------------------------------------------------------------------------- |
40 // CpuFeatures utilities (for V8 compatibility). | 40 // CpuFeatures utilities (for V8 compatibility). |
41 | 41 |
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142 | 142 |
143 // Drop jssp as the stack pointer doesn't need to be included. | 143 // Drop jssp as the stack pointer doesn't need to be included. |
144 list.Remove(28); | 144 list.Remove(28); |
145 | 145 |
146 // Add the link register (x30) to the safepoint list. | 146 // Add the link register (x30) to the safepoint list. |
147 list.Combine(30); | 147 list.Combine(30); |
148 | 148 |
149 return list; | 149 return list; |
150 } | 150 } |
151 | 151 |
| 152 |
152 // ----------------------------------------------------------------------------- | 153 // ----------------------------------------------------------------------------- |
153 // Implementation of RelocInfo | 154 // Implementation of RelocInfo |
154 | 155 |
155 const int RelocInfo::kApplyMask = 0; | 156 const int RelocInfo::kApplyMask = 0; |
156 | 157 |
157 | 158 |
158 bool RelocInfo::IsCodedSpecially() { | 159 bool RelocInfo::IsCodedSpecially() { |
159 // The deserializer needs to know whether a pointer is specially coded. Being | 160 // The deserializer needs to know whether a pointer is specially coded. Being |
160 // specially coded on A64 means that it is a movz/movk sequence. We don't | 161 // specially coded on A64 means that it is a movz/movk sequence. We don't |
161 // generate those for relocatable pointers. | 162 // generate those for relocatable pointers. |
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1328 // Moves involving the stack pointer are encoded as add immediate with | 1329 // Moves involving the stack pointer are encoded as add immediate with |
1329 // second operand of zero. Otherwise, orr with first operand zr is | 1330 // second operand of zero. Otherwise, orr with first operand zr is |
1330 // used. | 1331 // used. |
1331 if (rd.IsSP() || rm.IsSP()) { | 1332 if (rd.IsSP() || rm.IsSP()) { |
1332 add(rd, rm, 0); | 1333 add(rd, rm, 0); |
1333 } else { | 1334 } else { |
1334 orr(rd, AppropriateZeroRegFor(rd), rm); | 1335 orr(rd, AppropriateZeroRegFor(rd), rm); |
1335 } | 1336 } |
1336 } | 1337 } |
1337 | 1338 |
| 1339 |
1338 void Assembler::mvn(const Register& rd, const Operand& operand) { | 1340 void Assembler::mvn(const Register& rd, const Operand& operand) { |
1339 orn(rd, AppropriateZeroRegFor(rd), operand); | 1341 orn(rd, AppropriateZeroRegFor(rd), operand); |
1340 } | 1342 } |
1341 | 1343 |
1342 | 1344 |
1343 void Assembler::mrs(const Register& rt, SystemRegister sysreg) { | 1345 void Assembler::mrs(const Register& rt, SystemRegister sysreg) { |
1344 ASSERT(rt.Is64Bits()); | 1346 ASSERT(rt.Is64Bits()); |
1345 Emit(MRS | ImmSystemRegister(sysreg) | Rt(rt)); | 1347 Emit(MRS | ImmSystemRegister(sysreg) | Rt(rt)); |
1346 } | 1348 } |
1347 | 1349 |
1348 | 1350 |
1349 void Assembler::msr(SystemRegister sysreg, const Register& rt) { | 1351 void Assembler::msr(SystemRegister sysreg, const Register& rt) { |
1350 ASSERT(rt.Is64Bits()); | 1352 ASSERT(rt.Is64Bits()); |
1351 Emit(MSR | Rt(rt) | ImmSystemRegister(sysreg)); | 1353 Emit(MSR | Rt(rt) | ImmSystemRegister(sysreg)); |
1352 } | 1354 } |
1353 | 1355 |
1354 | 1356 |
1355 void Assembler::hint(SystemHint code) { | 1357 void Assembler::hint(SystemHint code) { |
1356 Emit(HINT | ImmHint(code) | Rt(xzr)); | 1358 Emit(HINT | ImmHint(code) | Rt(xzr)); |
1357 } | 1359 } |
1358 | 1360 |
| 1361 |
1359 void Assembler::dmb(BarrierDomain domain, BarrierType type) { | 1362 void Assembler::dmb(BarrierDomain domain, BarrierType type) { |
1360 Emit(DMB | ImmBarrierDomain(domain) | ImmBarrierType(type)); | 1363 Emit(DMB | ImmBarrierDomain(domain) | ImmBarrierType(type)); |
1361 } | 1364 } |
1362 | 1365 |
| 1366 |
1363 void Assembler::dsb(BarrierDomain domain, BarrierType type) { | 1367 void Assembler::dsb(BarrierDomain domain, BarrierType type) { |
1364 Emit(DSB | ImmBarrierDomain(domain) | ImmBarrierType(type)); | 1368 Emit(DSB | ImmBarrierDomain(domain) | ImmBarrierType(type)); |
1365 } | 1369 } |
1366 | 1370 |
| 1371 |
1367 void Assembler::isb() { | 1372 void Assembler::isb() { |
1368 Emit(ISB | ImmBarrierDomain(FullSystem) | ImmBarrierType(BarrierAll)); | 1373 Emit(ISB | ImmBarrierDomain(FullSystem) | ImmBarrierType(BarrierAll)); |
1369 } | 1374 } |
1370 | 1375 |
| 1376 |
1371 void Assembler::fmov(FPRegister fd, double imm) { | 1377 void Assembler::fmov(FPRegister fd, double imm) { |
1372 if (fd.Is64Bits() && IsImmFP64(imm)) { | 1378 if (fd.Is64Bits() && IsImmFP64(imm)) { |
1373 Emit(FMOV_d_imm | Rd(fd) | ImmFP64(imm)); | 1379 Emit(FMOV_d_imm | Rd(fd) | ImmFP64(imm)); |
1374 } else if (fd.Is32Bits() && IsImmFP32(imm)) { | 1380 } else if (fd.Is32Bits() && IsImmFP32(imm)) { |
1375 Emit(FMOV_s_imm | Rd(fd) | ImmFP32(static_cast<float>(imm))); | 1381 Emit(FMOV_s_imm | Rd(fd) | ImmFP32(static_cast<float>(imm))); |
1376 } else if ((imm == 0.0) && (copysign(1.0, imm) == 1.0)) { | 1382 } else if ((imm == 0.0) && (copysign(1.0, imm) == 1.0)) { |
1377 Register zr = AppropriateZeroRegFor(fd); | 1383 Register zr = AppropriateZeroRegFor(fd); |
1378 fmov(fd, zr); | 1384 fmov(fd, zr); |
1379 } else { | 1385 } else { |
1380 ldr(fd, imm); | 1386 ldr(fd, imm); |
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2194 set_bits >>= 1; | 2200 set_bits >>= 1; |
2195 imm_s_fixed >>= 1; | 2201 imm_s_fixed >>= 1; |
2196 continue; | 2202 continue; |
2197 } | 2203 } |
2198 | 2204 |
2199 // 6. Otherwise, the value can't be encoded. | 2205 // 6. Otherwise, the value can't be encoded. |
2200 return false; | 2206 return false; |
2201 } | 2207 } |
2202 } | 2208 } |
2203 | 2209 |
| 2210 |
2204 bool Assembler::IsImmConditionalCompare(int64_t immediate) { | 2211 bool Assembler::IsImmConditionalCompare(int64_t immediate) { |
2205 return is_uint5(immediate); | 2212 return is_uint5(immediate); |
2206 } | 2213 } |
2207 | 2214 |
2208 | 2215 |
2209 bool Assembler::IsImmFP32(float imm) { | 2216 bool Assembler::IsImmFP32(float imm) { |
2210 // Valid values will have the form: | 2217 // Valid values will have the form: |
2211 // aBbb.bbbc.defg.h000.0000.0000.0000.0000 | 2218 // aBbb.bbbc.defg.h000.0000.0000.0000.0000 |
2212 uint32_t bits = float_to_rawbits(imm); | 2219 uint32_t bits = float_to_rawbits(imm); |
2213 // bits[19..0] are cleared. | 2220 // bits[19..0] are cleared. |
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2509 // code. | 2516 // code. |
2510 #ifdef ENABLE_DEBUGGER_SUPPORT | 2517 #ifdef ENABLE_DEBUGGER_SUPPORT |
2511 RecordRelocInfo(RelocInfo::CONST_POOL, static_cast<intptr_t>(size)); | 2518 RecordRelocInfo(RelocInfo::CONST_POOL, static_cast<intptr_t>(size)); |
2512 #endif | 2519 #endif |
2513 } | 2520 } |
2514 | 2521 |
2515 | 2522 |
2516 } } // namespace v8::internal | 2523 } } // namespace v8::internal |
2517 | 2524 |
2518 #endif // V8_TARGET_ARCH_A64 | 2525 #endif // V8_TARGET_ARCH_A64 |
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