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Side by Side Diff: src/mips64/macro-assembler-mips64.h

Issue 1485023004: MIPS:[turbofan] Use Ins, Dins to clear bits instead of And with inverted immediate. (Closed) Base URL: https://chromium.googlesource.com/v8/v8.git@master
Patch Set: Fix comments. Created 5 years ago
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1 // Copyright 2012 the V8 project authors. All rights reserved. 1 // Copyright 2012 the V8 project authors. All rights reserved.
2 // Use of this source code is governed by a BSD-style license that can be 2 // Use of this source code is governed by a BSD-style license that can be
3 // found in the LICENSE file. 3 // found in the LICENSE file.
4 4
5 #ifndef V8_MIPS_MACRO_ASSEMBLER_MIPS_H_ 5 #ifndef V8_MIPS_MACRO_ASSEMBLER_MIPS_H_
6 #define V8_MIPS_MACRO_ASSEMBLER_MIPS_H_ 6 #define V8_MIPS_MACRO_ASSEMBLER_MIPS_H_
7 7
8 #include "src/assembler.h" 8 #include "src/assembler.h"
9 #include "src/globals.h" 9 #include "src/globals.h"
10 #include "src/mips64/assembler-mips64.h" 10 #include "src/mips64/assembler-mips64.h"
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798 void PopSafepointRegisters(); 798 void PopSafepointRegisters();
799 // Store value in register src in the safepoint stack slot for 799 // Store value in register src in the safepoint stack slot for
800 // register dst. 800 // register dst.
801 void StoreToSafepointRegisterSlot(Register src, Register dst); 801 void StoreToSafepointRegisterSlot(Register src, Register dst);
802 // Load the value of the src register from its safepoint stack slot 802 // Load the value of the src register from its safepoint stack slot
803 // into register dst. 803 // into register dst.
804 void LoadFromSafepointRegisterSlot(Register dst, Register src); 804 void LoadFromSafepointRegisterSlot(Register dst, Register src);
805 805
806 // MIPS64 R2 instruction macro. 806 // MIPS64 R2 instruction macro.
807 void Ins(Register rt, Register rs, uint16_t pos, uint16_t size); 807 void Ins(Register rt, Register rs, uint16_t pos, uint16_t size);
808 void Dins(Register rt, Register rs, uint16_t pos, uint16_t size);
808 void Ext(Register rt, Register rs, uint16_t pos, uint16_t size); 809 void Ext(Register rt, Register rs, uint16_t pos, uint16_t size);
809 void Dext(Register rt, Register rs, uint16_t pos, uint16_t size); 810 void Dext(Register rt, Register rs, uint16_t pos, uint16_t size);
810 811
811 // --------------------------------------------------------------------------- 812 // ---------------------------------------------------------------------------
812 // FPU macros. These do not handle special cases like NaN or +- inf. 813 // FPU macros. These do not handle special cases like NaN or +- inf.
813 814
814 // Convert unsigned word to double. 815 // Convert unsigned word to double.
815 void Cvt_d_uw(FPURegister fd, FPURegister fs); 816 void Cvt_d_uw(FPURegister fd, FPURegister fs);
816 void Cvt_d_uw(FPURegister fd, Register rs); 817 void Cvt_d_uw(FPURegister fd, Register rs);
817 818
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1848 #define __FILE_LINE__ __FILE__ ":" CODE_COVERAGE_TOSTRING(__LINE__) 1849 #define __FILE_LINE__ __FILE__ ":" CODE_COVERAGE_TOSTRING(__LINE__)
1849 #define ACCESS_MASM(masm) masm->stop(__FILE_LINE__); masm-> 1850 #define ACCESS_MASM(masm) masm->stop(__FILE_LINE__); masm->
1850 #else 1851 #else
1851 #define ACCESS_MASM(masm) masm-> 1852 #define ACCESS_MASM(masm) masm->
1852 #endif 1853 #endif
1853 1854
1854 } // namespace internal 1855 } // namespace internal
1855 } // namespace v8 1856 } // namespace v8
1856 1857
1857 #endif // V8_MIPS_MACRO_ASSEMBLER_MIPS_H_ 1858 #endif // V8_MIPS_MACRO_ASSEMBLER_MIPS_H_
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