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Side by Side Diff: src/compiler/mips64/instruction-codes-mips64.h

Issue 1485023004: MIPS:[turbofan] Use Ins, Dins to clear bits instead of And with inverted immediate. (Closed) Base URL: https://chromium.googlesource.com/v8/v8.git@master
Patch Set: Fix comments. Created 5 years ago
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1 // Copyright 2014 the V8 project authors. All rights reserved. 1 // Copyright 2014 the V8 project authors. All rights reserved.
2 // Use of this source code is governed by a BSD-style license that can be 2 // Use of this source code is governed by a BSD-style license that can be
3 // found in the LICENSE file. 3 // found in the LICENSE file.
4 4
5 #ifndef V8_COMPILER_MIPS_INSTRUCTION_CODES_MIPS_H_ 5 #ifndef V8_COMPILER_MIPS_INSTRUCTION_CODES_MIPS_H_
6 #define V8_COMPILER_MIPS_INSTRUCTION_CODES_MIPS_H_ 6 #define V8_COMPILER_MIPS_INSTRUCTION_CODES_MIPS_H_
7 7
8 namespace v8 { 8 namespace v8 {
9 namespace internal { 9 namespace internal {
10 namespace compiler { 10 namespace compiler {
(...skipping 20 matching lines...) Expand all
31 V(Mips64DmodU) \ 31 V(Mips64DmodU) \
32 V(Mips64And) \ 32 V(Mips64And) \
33 V(Mips64Or) \ 33 V(Mips64Or) \
34 V(Mips64Nor) \ 34 V(Mips64Nor) \
35 V(Mips64Xor) \ 35 V(Mips64Xor) \
36 V(Mips64Clz) \ 36 V(Mips64Clz) \
37 V(Mips64Shl) \ 37 V(Mips64Shl) \
38 V(Mips64Shr) \ 38 V(Mips64Shr) \
39 V(Mips64Sar) \ 39 V(Mips64Sar) \
40 V(Mips64Ext) \ 40 V(Mips64Ext) \
41 V(Mips64Ins) \
41 V(Mips64Dext) \ 42 V(Mips64Dext) \
43 V(Mips64Dins) \
42 V(Mips64Dclz) \ 44 V(Mips64Dclz) \
43 V(Mips64Dshl) \ 45 V(Mips64Dshl) \
44 V(Mips64Dshr) \ 46 V(Mips64Dshr) \
45 V(Mips64Dsar) \ 47 V(Mips64Dsar) \
46 V(Mips64Ror) \ 48 V(Mips64Ror) \
47 V(Mips64Dror) \ 49 V(Mips64Dror) \
48 V(Mips64Mov) \ 50 V(Mips64Mov) \
49 V(Mips64Tst) \ 51 V(Mips64Tst) \
50 V(Mips64Cmp) \ 52 V(Mips64Cmp) \
51 V(Mips64CmpS) \ 53 V(Mips64CmpS) \
(...skipping 84 matching lines...) Expand 10 before | Expand all | Expand 10 after
136 #define TARGET_ADDRESSING_MODE_LIST(V) \ 138 #define TARGET_ADDRESSING_MODE_LIST(V) \
137 V(MRI) /* [%r0 + K] */ \ 139 V(MRI) /* [%r0 + K] */ \
138 V(MRR) /* [%r0 + %r1] */ 140 V(MRR) /* [%r0 + %r1] */
139 141
140 142
141 } // namespace compiler 143 } // namespace compiler
142 } // namespace internal 144 } // namespace internal
143 } // namespace v8 145 } // namespace v8
144 146
145 #endif // V8_COMPILER_MIPS_INSTRUCTION_CODES_MIPS_H_ 147 #endif // V8_COMPILER_MIPS_INSTRUCTION_CODES_MIPS_H_
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