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| 1 // Copyright 2013 the V8 project authors. All rights reserved. |
| 2 // Redistribution and use in source and binary forms, with or without |
| 3 // modification, are permitted provided that the following conditions are |
| 4 // met: |
| 5 // |
| 6 // * Redistributions of source code must retain the above copyright |
| 7 // notice, this list of conditions and the following disclaimer. |
| 8 // * Redistributions in binary form must reproduce the above |
| 9 // copyright notice, this list of conditions and the following |
| 10 // disclaimer in the documentation and/or other materials provided |
| 11 // with the distribution. |
| 12 // * Neither the name of Google Inc. nor the names of its |
| 13 // contributors may be used to endorse or promote products derived |
| 14 // from this software without specific prior written permission. |
| 15 // |
| 16 // THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS |
| 17 // "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT |
| 18 // LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR |
| 19 // A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT |
| 20 // OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, |
| 21 // SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT |
| 22 // LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, |
| 23 // DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY |
| 24 // THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
| 25 // (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE |
| 26 // OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
| 27 |
| 28 #ifndef V8_A64_CONSTANTS_A64_H_ |
| 29 #define V8_A64_CONSTANTS_A64_H_ |
| 30 |
| 31 |
| 32 // Assert that this is an LP64 system. |
| 33 STATIC_ASSERT(sizeof(int) == sizeof(int32_t)); // NOLINT(runtime/sizeof) |
| 34 STATIC_ASSERT(sizeof(long) == sizeof(int64_t)); // NOLINT(runtime/int) |
| 35 STATIC_ASSERT(sizeof(void *) == sizeof(int64_t)); // NOLINT(runtime/sizeof) |
| 36 STATIC_ASSERT(sizeof(1) == sizeof(int32_t)); // NOLINT(runtime/sizeof) |
| 37 STATIC_ASSERT(sizeof(1L) == sizeof(int64_t)); // NOLINT(runtime/sizeof) |
| 38 |
| 39 |
| 40 // Get the standard printf format macros for C99 stdint types. |
| 41 #define __STDC_FORMAT_MACROS |
| 42 #include <inttypes.h> |
| 43 |
| 44 |
| 45 namespace v8 { |
| 46 namespace internal { |
| 47 |
| 48 |
| 49 const unsigned kInstructionSize = 4; |
| 50 const unsigned kInstructionSizeLog2 = 2; |
| 51 const unsigned kLiteralEntrySize = 4; |
| 52 const unsigned kLiteralEntrySizeLog2 = 2; |
| 53 const unsigned kMaxLoadLiteralRange = 1 * MB; |
| 54 |
| 55 const unsigned kNumberOfRegisters = 32; |
| 56 const unsigned kNumberOfFPRegisters = 32; |
| 57 // Callee saved registers are x19-x30(lr). |
| 58 const int kNumberOfCalleeSavedRegisters = 11; |
| 59 const int kFirstCalleeSavedRegisterIndex = 19; |
| 60 // Callee saved FP registers are d8-d15. |
| 61 const int kNumberOfCalleeSavedFPRegisters = 8; |
| 62 const int kFirstCalleeSavedFPRegisterIndex = 8; |
| 63 // Callee saved registers with no specific purpose in JS are x19-x25. |
| 64 const unsigned kJSCalleeSavedRegList = 0x03f80000; |
| 65 // TODO(all): k<Y>RegSize should probably be k<Y>RegSizeInBits. |
| 66 const unsigned kWRegSize = 32; |
| 67 const unsigned kWRegSizeLog2 = 5; |
| 68 const unsigned kWRegSizeInBytes = kWRegSize >> 3; |
| 69 const unsigned kWRegSizeInBytesLog2 = kWRegSizeLog2 - 3; |
| 70 const unsigned kXRegSize = 64; |
| 71 const unsigned kXRegSizeLog2 = 6; |
| 72 const unsigned kXRegSizeInBytes = kXRegSize >> 3; |
| 73 const unsigned kXRegSizeInBytesLog2 = kXRegSizeLog2 - 3; |
| 74 const unsigned kSRegSize = 32; |
| 75 const unsigned kSRegSizeLog2 = 5; |
| 76 const unsigned kSRegSizeInBytes = kSRegSize >> 3; |
| 77 const unsigned kSRegSizeInBytesLog2 = kSRegSizeLog2 - 3; |
| 78 const unsigned kDRegSize = 64; |
| 79 const unsigned kDRegSizeLog2 = 6; |
| 80 const unsigned kDRegSizeInBytes = kDRegSize >> 3; |
| 81 const unsigned kDRegSizeInBytesLog2 = kDRegSizeLog2 - 3; |
| 82 const int64_t kWRegMask = 0x00000000ffffffffL; |
| 83 const int64_t kXRegMask = 0xffffffffffffffffL; |
| 84 const int64_t kSRegMask = 0x00000000ffffffffL; |
| 85 const int64_t kDRegMask = 0xffffffffffffffffL; |
| 86 // TODO(all) check if the expression below works on all compilers or if it |
| 87 // triggers an overflow error. |
| 88 const int64_t kDSignMask = 0x1L << 63; |
| 89 const int64_t kDSignBit = 63; |
| 90 const int64_t kXSignMask = 0x1L << 63; |
| 91 const int64_t kXSignBit = 63; |
| 92 const int64_t kWSignMask = 0x1L << 31; |
| 93 const int64_t kWSignBit = 31; |
| 94 const int64_t kByteMask = 0xffL; |
| 95 const int64_t kHalfWordMask = 0xffffL; |
| 96 const int64_t kWordMask = 0xffffffffL; |
| 97 const uint64_t kXMaxUInt = 0xffffffffffffffffUL; |
| 98 const uint64_t kWMaxUInt = 0xffffffffUL; |
| 99 const int64_t kXMaxInt = 0x7fffffffffffffffL; |
| 100 const int64_t kXMinInt = 0x8000000000000000L; |
| 101 const int32_t kWMaxInt = 0x7fffffff; |
| 102 const int32_t kWMinInt = 0x80000000; |
| 103 const unsigned kFramePointerRegCode = 29; |
| 104 const unsigned kLinkRegCode = 30; |
| 105 const unsigned kZeroRegCode = 31; |
| 106 const unsigned kJSSPCode = 28; |
| 107 const unsigned kSPRegInternalCode = 63; |
| 108 const unsigned kRegCodeMask = 0x1f; |
| 109 // Standard machine types defined by AAPCS64. |
| 110 const unsigned kByteSize = 8; |
| 111 const unsigned kByteSizeInBytes = kByteSize >> 3; |
| 112 const unsigned kHalfWordSize = 16; |
| 113 const unsigned kHalfWordSizeLog2 = 4; |
| 114 const unsigned kHalfWordSizeInBytes = kHalfWordSize >> 3; |
| 115 const unsigned kHalfWordSizeInBytesLog2 = kHalfWordSizeLog2 - 3; |
| 116 const unsigned kWordSize = 32; |
| 117 const unsigned kWordSizeLog2 = 5; |
| 118 const unsigned kWordSizeInBytes = kWordSize >> 3; |
| 119 const unsigned kWordSizeInBytesLog2 = kWordSizeLog2 - 3; |
| 120 const unsigned kDoubleWordSize = 64; |
| 121 const unsigned kDoubleWordSizeInBytes = kDoubleWordSize >> 3; |
| 122 const unsigned kQuadWordSize = 128; |
| 123 const unsigned kQuadWordSizeInBytes = kQuadWordSize >> 3; |
| 124 // AArch64 floating-point specifics. These match IEEE-754. |
| 125 const unsigned kDoubleMantissaBits = 52; |
| 126 const unsigned kDoubleExponentBits = 11; |
| 127 const unsigned kFloatMantissaBits = 23; |
| 128 const unsigned kFloatExponentBits = 8; |
| 129 |
| 130 #define REGISTER_CODE_LIST(R) \ |
| 131 R(0) R(1) R(2) R(3) R(4) R(5) R(6) R(7) \ |
| 132 R(8) R(9) R(10) R(11) R(12) R(13) R(14) R(15) \ |
| 133 R(16) R(17) R(18) R(19) R(20) R(21) R(22) R(23) \ |
| 134 R(24) R(25) R(26) R(27) R(28) R(29) R(30) R(31) |
| 135 |
| 136 #define INSTRUCTION_FIELDS_LIST(V_) \ |
| 137 /* Register fields */ \ |
| 138 V_(Rd, 4, 0, Bits) /* Destination register. */ \ |
| 139 V_(Rn, 9, 5, Bits) /* First source register. */ \ |
| 140 V_(Rm, 20, 16, Bits) /* Second source register. */ \ |
| 141 V_(Ra, 14, 10, Bits) /* Third source register. */ \ |
| 142 V_(Rt, 4, 0, Bits) /* Load dest / store source. */ \ |
| 143 V_(Rt2, 14, 10, Bits) /* Load second dest / */ \ |
| 144 /* store second source. */ \ |
| 145 V_(PrefetchMode, 4, 0, Bits) \ |
| 146 \ |
| 147 /* Common bits */ \ |
| 148 V_(SixtyFourBits, 31, 31, Bits) \ |
| 149 V_(FlagsUpdate, 29, 29, Bits) \ |
| 150 \ |
| 151 /* PC relative addressing */ \ |
| 152 V_(ImmPCRelHi, 23, 5, SignedBits) \ |
| 153 V_(ImmPCRelLo, 30, 29, Bits) \ |
| 154 \ |
| 155 /* Add/subtract/logical shift register */ \ |
| 156 V_(ShiftDP, 23, 22, Bits) \ |
| 157 V_(ImmDPShift, 15, 10, Bits) \ |
| 158 \ |
| 159 /* Add/subtract immediate */ \ |
| 160 V_(ImmAddSub, 21, 10, Bits) \ |
| 161 V_(ShiftAddSub, 23, 22, Bits) \ |
| 162 \ |
| 163 /* Add/substract extend */ \ |
| 164 V_(ImmExtendShift, 12, 10, Bits) \ |
| 165 V_(ExtendMode, 15, 13, Bits) \ |
| 166 \ |
| 167 /* Move wide */ \ |
| 168 V_(ImmMoveWide, 20, 5, Bits) \ |
| 169 V_(ShiftMoveWide, 22, 21, Bits) \ |
| 170 \ |
| 171 /* Logical immediate, bitfield and extract */ \ |
| 172 V_(BitN, 22, 22, Bits) \ |
| 173 V_(ImmRotate, 21, 16, Bits) \ |
| 174 V_(ImmSetBits, 15, 10, Bits) \ |
| 175 V_(ImmR, 21, 16, Bits) \ |
| 176 V_(ImmS, 15, 10, Bits) \ |
| 177 \ |
| 178 /* Test and branch immediate */ \ |
| 179 V_(ImmTestBranch, 18, 5, SignedBits) \ |
| 180 V_(ImmTestBranchBit40, 23, 19, Bits) \ |
| 181 V_(ImmTestBranchBit5, 31, 31, Bits) \ |
| 182 \ |
| 183 /* Conditionals */ \ |
| 184 V_(Condition, 15, 12, Bits) \ |
| 185 V_(ConditionBranch, 3, 0, Bits) \ |
| 186 V_(Nzcv, 3, 0, Bits) \ |
| 187 V_(ImmCondCmp, 20, 16, Bits) \ |
| 188 V_(ImmCondBranch, 23, 5, SignedBits) \ |
| 189 \ |
| 190 /* Floating point */ \ |
| 191 V_(FPType, 23, 22, Bits) \ |
| 192 V_(ImmFP, 20, 13, Bits) \ |
| 193 V_(FPScale, 15, 10, Bits) \ |
| 194 \ |
| 195 /* Load Store */ \ |
| 196 V_(ImmLS, 20, 12, SignedBits) \ |
| 197 V_(ImmLSUnsigned, 21, 10, Bits) \ |
| 198 V_(ImmLSPair, 21, 15, SignedBits) \ |
| 199 V_(SizeLS, 31, 30, Bits) \ |
| 200 V_(ImmShiftLS, 12, 12, Bits) \ |
| 201 \ |
| 202 /* Other immediates */ \ |
| 203 V_(ImmUncondBranch, 25, 0, SignedBits) \ |
| 204 V_(ImmCmpBranch, 23, 5, SignedBits) \ |
| 205 V_(ImmLLiteral, 23, 5, SignedBits) \ |
| 206 V_(ImmException, 20, 5, Bits) \ |
| 207 V_(ImmHint, 11, 5, Bits) \ |
| 208 V_(ImmBarrierDomain, 11, 10, Bits) \ |
| 209 V_(ImmBarrierType, 9, 8, Bits) \ |
| 210 \ |
| 211 /* System (MRS, MSR) */ \ |
| 212 V_(ImmSystemRegister, 19, 5, Bits) \ |
| 213 V_(SysO0, 19, 19, Bits) \ |
| 214 V_(SysOp1, 18, 16, Bits) \ |
| 215 V_(SysOp2, 7, 5, Bits) \ |
| 216 V_(CRn, 15, 12, Bits) \ |
| 217 V_(CRm, 11, 8, Bits) \ |
| 218 |
| 219 |
| 220 #define SYSTEM_REGISTER_FIELDS_LIST(V_, M_) \ |
| 221 /* NZCV */ \ |
| 222 V_(Flags, 31, 28, Bits) \ |
| 223 V_(N, 31, 31, Bits) \ |
| 224 V_(Z, 30, 30, Bits) \ |
| 225 V_(C, 29, 29, Bits) \ |
| 226 V_(V, 28, 28, Bits) \ |
| 227 M_(NZCV, Flags_mask) \ |
| 228 \ |
| 229 /* FPCR */ \ |
| 230 V_(AHP, 26, 26, Bits) \ |
| 231 V_(DN, 25, 25, Bits) \ |
| 232 V_(FZ, 24, 24, Bits) \ |
| 233 V_(RMode, 23, 22, Bits) \ |
| 234 M_(FPCR, AHP_mask | DN_mask | FZ_mask | RMode_mask) |
| 235 |
| 236 |
| 237 // Fields offsets. |
| 238 #define DECLARE_FIELDS_OFFSETS(Name, HighBit, LowBit, X) \ |
| 239 const int Name##_offset = LowBit; \ |
| 240 const int Name##_width = HighBit - LowBit + 1; \ |
| 241 const uint32_t Name##_mask = ((1 << Name##_width) - 1) << LowBit; |
| 242 #define NOTHING(A, B) |
| 243 INSTRUCTION_FIELDS_LIST(DECLARE_FIELDS_OFFSETS) |
| 244 SYSTEM_REGISTER_FIELDS_LIST(DECLARE_FIELDS_OFFSETS, NOTHING) |
| 245 #undef NOTHING |
| 246 #undef DECLARE_FIELDS_BITS |
| 247 |
| 248 // ImmPCRel is a compound field (not present in INSTRUCTION_FIELDS_LIST), formed |
| 249 // from ImmPCRelLo and ImmPCRelHi. |
| 250 const int ImmPCRel_mask = ImmPCRelLo_mask | ImmPCRelHi_mask; |
| 251 |
| 252 // Condition codes. |
| 253 enum Condition { |
| 254 eq = 0, |
| 255 ne = 1, |
| 256 hs = 2, |
| 257 lo = 3, |
| 258 mi = 4, |
| 259 pl = 5, |
| 260 vs = 6, |
| 261 vc = 7, |
| 262 hi = 8, |
| 263 ls = 9, |
| 264 ge = 10, |
| 265 lt = 11, |
| 266 gt = 12, |
| 267 le = 13, |
| 268 al = 14, |
| 269 nv = 15 // Behaves as always/al. |
| 270 }; |
| 271 |
| 272 inline Condition InvertCondition(Condition cond) { |
| 273 // Conditions al and nv behave identically, as "always true". They can't be |
| 274 // inverted, because there is no never condition. |
| 275 ASSERT((cond != al) && (cond != nv)); |
| 276 return static_cast<Condition>(cond ^ 1); |
| 277 } |
| 278 |
| 279 // Corresponds to transposing the operands of a comparison. |
| 280 inline Condition ReverseConditionForCmp(Condition cond) { |
| 281 switch (cond) { |
| 282 case lo: |
| 283 return hi; |
| 284 case hi: |
| 285 return lo; |
| 286 case hs: |
| 287 return ls; |
| 288 case ls: |
| 289 return hs; |
| 290 case lt: |
| 291 return gt; |
| 292 case gt: |
| 293 return lt; |
| 294 case ge: |
| 295 return le; |
| 296 case le: |
| 297 return ge; |
| 298 case eq: |
| 299 return eq; |
| 300 default: |
| 301 // In practice this function is only used with a condition coming from |
| 302 // TokenToCondition in lithium-codegen-a64.cc. Any other condition is |
| 303 // invalid as it doesn't necessary make sense to reverse it (consider |
| 304 // 'mi' for instance). |
| 305 UNREACHABLE(); |
| 306 return nv; |
| 307 }; |
| 308 } |
| 309 |
| 310 enum FlagsUpdate { |
| 311 SetFlags = 1, |
| 312 LeaveFlags = 0 |
| 313 }; |
| 314 |
| 315 enum StatusFlags { |
| 316 NoFlag = 0, |
| 317 |
| 318 // Derive the flag combinations from the system register bit descriptions. |
| 319 NFlag = N_mask, |
| 320 ZFlag = Z_mask, |
| 321 CFlag = C_mask, |
| 322 VFlag = V_mask, |
| 323 NZFlag = NFlag | ZFlag, |
| 324 NCFlag = NFlag | CFlag, |
| 325 NVFlag = NFlag | VFlag, |
| 326 ZCFlag = ZFlag | CFlag, |
| 327 ZVFlag = ZFlag | VFlag, |
| 328 CVFlag = CFlag | VFlag, |
| 329 NZCFlag = NFlag | ZFlag | CFlag, |
| 330 NZVFlag = NFlag | ZFlag | VFlag, |
| 331 NCVFlag = NFlag | CFlag | VFlag, |
| 332 ZCVFlag = ZFlag | CFlag | VFlag, |
| 333 NZCVFlag = NFlag | ZFlag | CFlag | VFlag, |
| 334 |
| 335 // Floating-point comparison results. |
| 336 FPEqualFlag = ZCFlag, |
| 337 FPLessThanFlag = NFlag, |
| 338 FPGreaterThanFlag = CFlag, |
| 339 FPUnorderedFlag = CVFlag |
| 340 }; |
| 341 |
| 342 enum Shift { |
| 343 NO_SHIFT = -1, |
| 344 LSL = 0x0, |
| 345 LSR = 0x1, |
| 346 ASR = 0x2, |
| 347 ROR = 0x3 |
| 348 }; |
| 349 |
| 350 enum Extend { |
| 351 NO_EXTEND = -1, |
| 352 UXTB = 0, |
| 353 UXTH = 1, |
| 354 UXTW = 2, |
| 355 UXTX = 3, |
| 356 SXTB = 4, |
| 357 SXTH = 5, |
| 358 SXTW = 6, |
| 359 SXTX = 7 |
| 360 }; |
| 361 |
| 362 enum SystemHint { |
| 363 NOP = 0, |
| 364 YIELD = 1, |
| 365 WFE = 2, |
| 366 WFI = 3, |
| 367 SEV = 4, |
| 368 SEVL = 5 |
| 369 }; |
| 370 |
| 371 enum BarrierDomain { |
| 372 OuterShareable = 0, |
| 373 NonShareable = 1, |
| 374 InnerShareable = 2, |
| 375 FullSystem = 3 |
| 376 }; |
| 377 |
| 378 enum BarrierType { |
| 379 BarrierOther = 0, |
| 380 BarrierReads = 1, |
| 381 BarrierWrites = 2, |
| 382 BarrierAll = 3 |
| 383 }; |
| 384 |
| 385 // System/special register names. |
| 386 // This information is not encoded as one field but as the concatenation of |
| 387 // multiple fields (Op0<0>, Op1, Crn, Crm, Op2). |
| 388 enum SystemRegister { |
| 389 NZCV = ((0x1 << SysO0_offset) | |
| 390 (0x3 << SysOp1_offset) | |
| 391 (0x4 << CRn_offset) | |
| 392 (0x2 << CRm_offset) | |
| 393 (0x0 << SysOp2_offset)) >> ImmSystemRegister_offset, |
| 394 FPCR = ((0x1 << SysO0_offset) | |
| 395 (0x3 << SysOp1_offset) | |
| 396 (0x4 << CRn_offset) | |
| 397 (0x4 << CRm_offset) | |
| 398 (0x0 << SysOp2_offset)) >> ImmSystemRegister_offset |
| 399 }; |
| 400 |
| 401 // Instruction enumerations. |
| 402 // |
| 403 // These are the masks that define a class of instructions, and the list of |
| 404 // instructions within each class. Each enumeration has a Fixed, FMask and |
| 405 // Mask value. |
| 406 // |
| 407 // Fixed: The fixed bits in this instruction class. |
| 408 // FMask: The mask used to extract the fixed bits in the class. |
| 409 // Mask: The mask used to identify the instructions within a class. |
| 410 // |
| 411 // The enumerations can be used like this: |
| 412 // |
| 413 // ASSERT(instr->Mask(PCRelAddressingFMask) == PCRelAddressingFixed); |
| 414 // switch(instr->Mask(PCRelAddressingMask)) { |
| 415 // case ADR: Format("adr 'Xd, 'AddrPCRelByte"); break; |
| 416 // case ADRP: Format("adrp 'Xd, 'AddrPCRelPage"); break; |
| 417 // default: printf("Unknown instruction\n"); |
| 418 // } |
| 419 |
| 420 |
| 421 // Generic fields. |
| 422 enum GenericInstrField { |
| 423 SixtyFourBits = 0x80000000, |
| 424 ThirtyTwoBits = 0x00000000, |
| 425 FP32 = 0x00000000, |
| 426 FP64 = 0x00400000 |
| 427 }; |
| 428 |
| 429 // PC relative addressing. |
| 430 enum PCRelAddressingOp { |
| 431 PCRelAddressingFixed = 0x10000000, |
| 432 PCRelAddressingFMask = 0x1F000000, |
| 433 PCRelAddressingMask = 0x9F000000, |
| 434 ADR = PCRelAddressingFixed | 0x00000000, |
| 435 ADRP = PCRelAddressingFixed | 0x80000000 |
| 436 }; |
| 437 |
| 438 // Add/sub (immediate, shifted and extended.) |
| 439 const int kSFOffset = 31; |
| 440 enum AddSubOp { |
| 441 AddSubOpMask = 0x60000000, |
| 442 AddSubSetFlagsBit = 0x20000000, |
| 443 ADD = 0x00000000, |
| 444 ADDS = ADD | AddSubSetFlagsBit, |
| 445 SUB = 0x40000000, |
| 446 SUBS = SUB | AddSubSetFlagsBit |
| 447 }; |
| 448 |
| 449 #define ADD_SUB_OP_LIST(V) \ |
| 450 V(ADD), \ |
| 451 V(ADDS), \ |
| 452 V(SUB), \ |
| 453 V(SUBS) |
| 454 |
| 455 enum AddSubImmediateOp { |
| 456 AddSubImmediateFixed = 0x11000000, |
| 457 AddSubImmediateFMask = 0x1F000000, |
| 458 AddSubImmediateMask = 0xFF000000, |
| 459 #define ADD_SUB_IMMEDIATE(A) \ |
| 460 A##_w_imm = AddSubImmediateFixed | A, \ |
| 461 A##_x_imm = AddSubImmediateFixed | A | SixtyFourBits |
| 462 ADD_SUB_OP_LIST(ADD_SUB_IMMEDIATE) |
| 463 #undef ADD_SUB_IMMEDIATE |
| 464 }; |
| 465 |
| 466 enum AddSubShiftedOp { |
| 467 AddSubShiftedFixed = 0x0B000000, |
| 468 AddSubShiftedFMask = 0x1F200000, |
| 469 AddSubShiftedMask = 0xFF200000, |
| 470 #define ADD_SUB_SHIFTED(A) \ |
| 471 A##_w_shift = AddSubShiftedFixed | A, \ |
| 472 A##_x_shift = AddSubShiftedFixed | A | SixtyFourBits |
| 473 ADD_SUB_OP_LIST(ADD_SUB_SHIFTED) |
| 474 #undef ADD_SUB_SHIFTED |
| 475 }; |
| 476 |
| 477 enum AddSubExtendedOp { |
| 478 AddSubExtendedFixed = 0x0B200000, |
| 479 AddSubExtendedFMask = 0x1F200000, |
| 480 AddSubExtendedMask = 0xFFE00000, |
| 481 #define ADD_SUB_EXTENDED(A) \ |
| 482 A##_w_ext = AddSubExtendedFixed | A, \ |
| 483 A##_x_ext = AddSubExtendedFixed | A | SixtyFourBits |
| 484 ADD_SUB_OP_LIST(ADD_SUB_EXTENDED) |
| 485 #undef ADD_SUB_EXTENDED |
| 486 }; |
| 487 |
| 488 // Add/sub with carry. |
| 489 enum AddSubWithCarryOp { |
| 490 AddSubWithCarryFixed = 0x1A000000, |
| 491 AddSubWithCarryFMask = 0x1FE00000, |
| 492 AddSubWithCarryMask = 0xFFE0FC00, |
| 493 ADC_w = AddSubWithCarryFixed | ADD, |
| 494 ADC_x = AddSubWithCarryFixed | ADD | SixtyFourBits, |
| 495 ADC = ADC_w, |
| 496 ADCS_w = AddSubWithCarryFixed | ADDS, |
| 497 ADCS_x = AddSubWithCarryFixed | ADDS | SixtyFourBits, |
| 498 SBC_w = AddSubWithCarryFixed | SUB, |
| 499 SBC_x = AddSubWithCarryFixed | SUB | SixtyFourBits, |
| 500 SBC = SBC_w, |
| 501 SBCS_w = AddSubWithCarryFixed | SUBS, |
| 502 SBCS_x = AddSubWithCarryFixed | SUBS | SixtyFourBits |
| 503 }; |
| 504 |
| 505 |
| 506 // Logical (immediate and shifted register). |
| 507 enum LogicalOp { |
| 508 LogicalOpMask = 0x60200000, |
| 509 NOT = 0x00200000, |
| 510 AND = 0x00000000, |
| 511 BIC = AND | NOT, |
| 512 ORR = 0x20000000, |
| 513 ORN = ORR | NOT, |
| 514 EOR = 0x40000000, |
| 515 EON = EOR | NOT, |
| 516 ANDS = 0x60000000, |
| 517 BICS = ANDS | NOT |
| 518 }; |
| 519 |
| 520 // Logical immediate. |
| 521 enum LogicalImmediateOp { |
| 522 LogicalImmediateFixed = 0x12000000, |
| 523 LogicalImmediateFMask = 0x1F800000, |
| 524 LogicalImmediateMask = 0xFF800000, |
| 525 AND_w_imm = LogicalImmediateFixed | AND, |
| 526 AND_x_imm = LogicalImmediateFixed | AND | SixtyFourBits, |
| 527 ORR_w_imm = LogicalImmediateFixed | ORR, |
| 528 ORR_x_imm = LogicalImmediateFixed | ORR | SixtyFourBits, |
| 529 EOR_w_imm = LogicalImmediateFixed | EOR, |
| 530 EOR_x_imm = LogicalImmediateFixed | EOR | SixtyFourBits, |
| 531 ANDS_w_imm = LogicalImmediateFixed | ANDS, |
| 532 ANDS_x_imm = LogicalImmediateFixed | ANDS | SixtyFourBits |
| 533 }; |
| 534 |
| 535 // Logical shifted register. |
| 536 enum LogicalShiftedOp { |
| 537 LogicalShiftedFixed = 0x0A000000, |
| 538 LogicalShiftedFMask = 0x1F000000, |
| 539 LogicalShiftedMask = 0xFF200000, |
| 540 AND_w = LogicalShiftedFixed | AND, |
| 541 AND_x = LogicalShiftedFixed | AND | SixtyFourBits, |
| 542 AND_shift = AND_w, |
| 543 BIC_w = LogicalShiftedFixed | BIC, |
| 544 BIC_x = LogicalShiftedFixed | BIC | SixtyFourBits, |
| 545 BIC_shift = BIC_w, |
| 546 ORR_w = LogicalShiftedFixed | ORR, |
| 547 ORR_x = LogicalShiftedFixed | ORR | SixtyFourBits, |
| 548 ORR_shift = ORR_w, |
| 549 ORN_w = LogicalShiftedFixed | ORN, |
| 550 ORN_x = LogicalShiftedFixed | ORN | SixtyFourBits, |
| 551 ORN_shift = ORN_w, |
| 552 EOR_w = LogicalShiftedFixed | EOR, |
| 553 EOR_x = LogicalShiftedFixed | EOR | SixtyFourBits, |
| 554 EOR_shift = EOR_w, |
| 555 EON_w = LogicalShiftedFixed | EON, |
| 556 EON_x = LogicalShiftedFixed | EON | SixtyFourBits, |
| 557 EON_shift = EON_w, |
| 558 ANDS_w = LogicalShiftedFixed | ANDS, |
| 559 ANDS_x = LogicalShiftedFixed | ANDS | SixtyFourBits, |
| 560 ANDS_shift = ANDS_w, |
| 561 BICS_w = LogicalShiftedFixed | BICS, |
| 562 BICS_x = LogicalShiftedFixed | BICS | SixtyFourBits, |
| 563 BICS_shift = BICS_w |
| 564 }; |
| 565 |
| 566 // Move wide immediate. |
| 567 enum MoveWideImmediateOp { |
| 568 MoveWideImmediateFixed = 0x12800000, |
| 569 MoveWideImmediateFMask = 0x1F800000, |
| 570 MoveWideImmediateMask = 0xFF800000, |
| 571 MOVN = 0x00000000, |
| 572 MOVZ = 0x40000000, |
| 573 MOVK = 0x60000000, |
| 574 MOVN_w = MoveWideImmediateFixed | MOVN, |
| 575 MOVN_x = MoveWideImmediateFixed | MOVN | SixtyFourBits, |
| 576 MOVZ_w = MoveWideImmediateFixed | MOVZ, |
| 577 MOVZ_x = MoveWideImmediateFixed | MOVZ | SixtyFourBits, |
| 578 MOVK_w = MoveWideImmediateFixed | MOVK, |
| 579 MOVK_x = MoveWideImmediateFixed | MOVK | SixtyFourBits |
| 580 }; |
| 581 |
| 582 // Bitfield. |
| 583 const int kBitfieldNOffset = 22; |
| 584 enum BitfieldOp { |
| 585 BitfieldFixed = 0x13000000, |
| 586 BitfieldFMask = 0x1F800000, |
| 587 BitfieldMask = 0xFF800000, |
| 588 SBFM_w = BitfieldFixed | 0x00000000, |
| 589 SBFM_x = BitfieldFixed | 0x80000000, |
| 590 SBFM = SBFM_w, |
| 591 BFM_w = BitfieldFixed | 0x20000000, |
| 592 BFM_x = BitfieldFixed | 0xA0000000, |
| 593 BFM = BFM_w, |
| 594 UBFM_w = BitfieldFixed | 0x40000000, |
| 595 UBFM_x = BitfieldFixed | 0xC0000000, |
| 596 UBFM = UBFM_w |
| 597 // Bitfield N field. |
| 598 }; |
| 599 |
| 600 // Extract. |
| 601 enum ExtractOp { |
| 602 ExtractFixed = 0x13800000, |
| 603 ExtractFMask = 0x1F800000, |
| 604 ExtractMask = 0xFFA00000, |
| 605 EXTR_w = ExtractFixed | 0x00000000, |
| 606 EXTR_x = ExtractFixed | 0x80000000, |
| 607 EXTR = EXTR_w |
| 608 }; |
| 609 |
| 610 // Unconditional branch. |
| 611 enum UnconditionalBranchOp { |
| 612 UnconditionalBranchFixed = 0x14000000, |
| 613 UnconditionalBranchFMask = 0x7C000000, |
| 614 UnconditionalBranchMask = 0xFC000000, |
| 615 B = UnconditionalBranchFixed | 0x00000000, |
| 616 BL = UnconditionalBranchFixed | 0x80000000 |
| 617 }; |
| 618 |
| 619 // Unconditional branch to register. |
| 620 enum UnconditionalBranchToRegisterOp { |
| 621 UnconditionalBranchToRegisterFixed = 0xD6000000, |
| 622 UnconditionalBranchToRegisterFMask = 0xFE000000, |
| 623 UnconditionalBranchToRegisterMask = 0xFFFFFC1F, |
| 624 BR = UnconditionalBranchToRegisterFixed | 0x001F0000, |
| 625 BLR = UnconditionalBranchToRegisterFixed | 0x003F0000, |
| 626 RET = UnconditionalBranchToRegisterFixed | 0x005F0000 |
| 627 }; |
| 628 |
| 629 // Compare and branch. |
| 630 enum CompareBranchOp { |
| 631 CompareBranchFixed = 0x34000000, |
| 632 CompareBranchFMask = 0x7E000000, |
| 633 CompareBranchMask = 0xFF000000, |
| 634 CBZ_w = CompareBranchFixed | 0x00000000, |
| 635 CBZ_x = CompareBranchFixed | 0x80000000, |
| 636 CBZ = CBZ_w, |
| 637 CBNZ_w = CompareBranchFixed | 0x01000000, |
| 638 CBNZ_x = CompareBranchFixed | 0x81000000, |
| 639 CBNZ = CBNZ_w |
| 640 }; |
| 641 |
| 642 // Test and branch. |
| 643 enum TestBranchOp { |
| 644 TestBranchFixed = 0x36000000, |
| 645 TestBranchFMask = 0x7E000000, |
| 646 TestBranchMask = 0x7F000000, |
| 647 TBZ = TestBranchFixed | 0x00000000, |
| 648 TBNZ = TestBranchFixed | 0x01000000 |
| 649 }; |
| 650 |
| 651 // Conditional branch. |
| 652 enum ConditionalBranchOp { |
| 653 ConditionalBranchFixed = 0x54000000, |
| 654 ConditionalBranchFMask = 0xFE000000, |
| 655 ConditionalBranchMask = 0xFF000010, |
| 656 B_cond = ConditionalBranchFixed | 0x00000000 |
| 657 }; |
| 658 |
| 659 // System. |
| 660 // System instruction encoding is complicated because some instructions use op |
| 661 // and CR fields to encode parameters. To handle this cleanly, the system |
| 662 // instructions are split into more than one enum. |
| 663 |
| 664 enum SystemOp { |
| 665 SystemFixed = 0xD5000000, |
| 666 SystemFMask = 0xFFC00000 |
| 667 }; |
| 668 |
| 669 enum SystemSysRegOp { |
| 670 SystemSysRegFixed = 0xD5100000, |
| 671 SystemSysRegFMask = 0xFFD00000, |
| 672 SystemSysRegMask = 0xFFF00000, |
| 673 MRS = SystemSysRegFixed | 0x00200000, |
| 674 MSR = SystemSysRegFixed | 0x00000000 |
| 675 }; |
| 676 |
| 677 enum SystemHintOp { |
| 678 SystemHintFixed = 0xD503201F, |
| 679 SystemHintFMask = 0xFFFFF01F, |
| 680 SystemHintMask = 0xFFFFF01F, |
| 681 HINT = SystemHintFixed | 0x00000000 |
| 682 }; |
| 683 |
| 684 // Exception. |
| 685 enum ExceptionOp { |
| 686 ExceptionFixed = 0xD4000000, |
| 687 ExceptionFMask = 0xFF000000, |
| 688 ExceptionMask = 0xFFE0001F, |
| 689 HLT = ExceptionFixed | 0x00400000, |
| 690 BRK = ExceptionFixed | 0x00200000, |
| 691 SVC = ExceptionFixed | 0x00000001, |
| 692 HVC = ExceptionFixed | 0x00000002, |
| 693 SMC = ExceptionFixed | 0x00000003, |
| 694 DCPS1 = ExceptionFixed | 0x00A00001, |
| 695 DCPS2 = ExceptionFixed | 0x00A00002, |
| 696 DCPS3 = ExceptionFixed | 0x00A00003 |
| 697 }; |
| 698 // Code used to spot hlt instructions that should not be hit. |
| 699 const int kHltBadCode = 0xbad; |
| 700 |
| 701 enum MemBarrierOp { |
| 702 MemBarrierFixed = 0xD503309F, |
| 703 MemBarrierFMask = 0xFFFFF09F, |
| 704 MemBarrierMask = 0xFFFFF0FF, |
| 705 DSB = MemBarrierFixed | 0x00000000, |
| 706 DMB = MemBarrierFixed | 0x00000020, |
| 707 ISB = MemBarrierFixed | 0x00000040 |
| 708 }; |
| 709 |
| 710 // Any load or store (including pair). |
| 711 enum LoadStoreAnyOp { |
| 712 LoadStoreAnyFMask = 0x0a000000, |
| 713 LoadStoreAnyFixed = 0x08000000 |
| 714 }; |
| 715 |
| 716 // Any load pair or store pair. |
| 717 enum LoadStorePairAnyOp { |
| 718 LoadStorePairAnyFMask = 0x3a000000, |
| 719 LoadStorePairAnyFixed = 0x28000000 |
| 720 }; |
| 721 |
| 722 #define LOAD_STORE_PAIR_OP_LIST(V) \ |
| 723 V(STP, w, 0x00000000), \ |
| 724 V(LDP, w, 0x00400000), \ |
| 725 V(LDPSW, x, 0x40400000), \ |
| 726 V(STP, x, 0x80000000), \ |
| 727 V(LDP, x, 0x80400000), \ |
| 728 V(STP, s, 0x04000000), \ |
| 729 V(LDP, s, 0x04400000), \ |
| 730 V(STP, d, 0x44000000), \ |
| 731 V(LDP, d, 0x44400000) |
| 732 |
| 733 // Load/store pair (post, pre and offset.) |
| 734 enum LoadStorePairOp { |
| 735 LoadStorePairMask = 0xC4400000, |
| 736 LoadStorePairLBit = 1 << 22, |
| 737 #define LOAD_STORE_PAIR(A, B, C) \ |
| 738 A##_##B = C |
| 739 LOAD_STORE_PAIR_OP_LIST(LOAD_STORE_PAIR) |
| 740 #undef LOAD_STORE_PAIR |
| 741 }; |
| 742 |
| 743 enum LoadStorePairPostIndexOp { |
| 744 LoadStorePairPostIndexFixed = 0x28800000, |
| 745 LoadStorePairPostIndexFMask = 0x3B800000, |
| 746 LoadStorePairPostIndexMask = 0xFFC00000, |
| 747 #define LOAD_STORE_PAIR_POST_INDEX(A, B, C) \ |
| 748 A##_##B##_post = LoadStorePairPostIndexFixed | A##_##B |
| 749 LOAD_STORE_PAIR_OP_LIST(LOAD_STORE_PAIR_POST_INDEX) |
| 750 #undef LOAD_STORE_PAIR_POST_INDEX |
| 751 }; |
| 752 |
| 753 enum LoadStorePairPreIndexOp { |
| 754 LoadStorePairPreIndexFixed = 0x29800000, |
| 755 LoadStorePairPreIndexFMask = 0x3B800000, |
| 756 LoadStorePairPreIndexMask = 0xFFC00000, |
| 757 #define LOAD_STORE_PAIR_PRE_INDEX(A, B, C) \ |
| 758 A##_##B##_pre = LoadStorePairPreIndexFixed | A##_##B |
| 759 LOAD_STORE_PAIR_OP_LIST(LOAD_STORE_PAIR_PRE_INDEX) |
| 760 #undef LOAD_STORE_PAIR_PRE_INDEX |
| 761 }; |
| 762 |
| 763 enum LoadStorePairOffsetOp { |
| 764 LoadStorePairOffsetFixed = 0x29000000, |
| 765 LoadStorePairOffsetFMask = 0x3B800000, |
| 766 LoadStorePairOffsetMask = 0xFFC00000, |
| 767 #define LOAD_STORE_PAIR_OFFSET(A, B, C) \ |
| 768 A##_##B##_off = LoadStorePairOffsetFixed | A##_##B |
| 769 LOAD_STORE_PAIR_OP_LIST(LOAD_STORE_PAIR_OFFSET) |
| 770 #undef LOAD_STORE_PAIR_OFFSET |
| 771 }; |
| 772 |
| 773 enum LoadStorePairNonTemporalOp { |
| 774 LoadStorePairNonTemporalFixed = 0x28000000, |
| 775 LoadStorePairNonTemporalFMask = 0x3B800000, |
| 776 LoadStorePairNonTemporalMask = 0xFFC00000, |
| 777 STNP_w = LoadStorePairNonTemporalFixed | STP_w, |
| 778 LDNP_w = LoadStorePairNonTemporalFixed | LDP_w, |
| 779 STNP_x = LoadStorePairNonTemporalFixed | STP_x, |
| 780 LDNP_x = LoadStorePairNonTemporalFixed | LDP_x, |
| 781 STNP_s = LoadStorePairNonTemporalFixed | STP_s, |
| 782 LDNP_s = LoadStorePairNonTemporalFixed | LDP_s, |
| 783 STNP_d = LoadStorePairNonTemporalFixed | STP_d, |
| 784 LDNP_d = LoadStorePairNonTemporalFixed | LDP_d |
| 785 }; |
| 786 |
| 787 // Load literal. |
| 788 enum LoadLiteralOp { |
| 789 LoadLiteralFixed = 0x18000000, |
| 790 LoadLiteralFMask = 0x3B000000, |
| 791 LoadLiteralMask = 0xFF000000, |
| 792 LDR_w_lit = LoadLiteralFixed | 0x00000000, |
| 793 LDR_x_lit = LoadLiteralFixed | 0x40000000, |
| 794 LDRSW_x_lit = LoadLiteralFixed | 0x80000000, |
| 795 PRFM_lit = LoadLiteralFixed | 0xC0000000, |
| 796 LDR_s_lit = LoadLiteralFixed | 0x04000000, |
| 797 LDR_d_lit = LoadLiteralFixed | 0x44000000 |
| 798 }; |
| 799 |
| 800 #define LOAD_STORE_OP_LIST(V) \ |
| 801 V(ST, RB, w, 0x00000000), \ |
| 802 V(ST, RH, w, 0x40000000), \ |
| 803 V(ST, R, w, 0x80000000), \ |
| 804 V(ST, R, x, 0xC0000000), \ |
| 805 V(LD, RB, w, 0x00400000), \ |
| 806 V(LD, RH, w, 0x40400000), \ |
| 807 V(LD, R, w, 0x80400000), \ |
| 808 V(LD, R, x, 0xC0400000), \ |
| 809 V(LD, RSB, x, 0x00800000), \ |
| 810 V(LD, RSH, x, 0x40800000), \ |
| 811 V(LD, RSW, x, 0x80800000), \ |
| 812 V(LD, RSB, w, 0x00C00000), \ |
| 813 V(LD, RSH, w, 0x40C00000), \ |
| 814 V(ST, R, s, 0x84000000), \ |
| 815 V(ST, R, d, 0xC4000000), \ |
| 816 V(LD, R, s, 0x84400000), \ |
| 817 V(LD, R, d, 0xC4400000) |
| 818 |
| 819 |
| 820 // Load/store unscaled offset. |
| 821 enum LoadStoreUnscaledOffsetOp { |
| 822 LoadStoreUnscaledOffsetFixed = 0x38000000, |
| 823 LoadStoreUnscaledOffsetFMask = 0x3B200C00, |
| 824 LoadStoreUnscaledOffsetMask = 0xFFE00C00, |
| 825 #define LOAD_STORE_UNSCALED(A, B, C, D) \ |
| 826 A##U##B##_##C = LoadStoreUnscaledOffsetFixed | D |
| 827 LOAD_STORE_OP_LIST(LOAD_STORE_UNSCALED) |
| 828 #undef LOAD_STORE_UNSCALED |
| 829 }; |
| 830 |
| 831 // Load/store (post, pre, offset and unsigned.) |
| 832 enum LoadStoreOp { |
| 833 LoadStoreOpMask = 0xC4C00000, |
| 834 #define LOAD_STORE(A, B, C, D) \ |
| 835 A##B##_##C = D |
| 836 LOAD_STORE_OP_LIST(LOAD_STORE), |
| 837 #undef LOAD_STORE |
| 838 PRFM = 0xC0800000 |
| 839 }; |
| 840 |
| 841 // Load/store post index. |
| 842 enum LoadStorePostIndex { |
| 843 LoadStorePostIndexFixed = 0x38000400, |
| 844 LoadStorePostIndexFMask = 0x3B200C00, |
| 845 LoadStorePostIndexMask = 0xFFE00C00, |
| 846 #define LOAD_STORE_POST_INDEX(A, B, C, D) \ |
| 847 A##B##_##C##_post = LoadStorePostIndexFixed | D |
| 848 LOAD_STORE_OP_LIST(LOAD_STORE_POST_INDEX) |
| 849 #undef LOAD_STORE_POST_INDEX |
| 850 }; |
| 851 |
| 852 // Load/store pre index. |
| 853 enum LoadStorePreIndex { |
| 854 LoadStorePreIndexFixed = 0x38000C00, |
| 855 LoadStorePreIndexFMask = 0x3B200C00, |
| 856 LoadStorePreIndexMask = 0xFFE00C00, |
| 857 #define LOAD_STORE_PRE_INDEX(A, B, C, D) \ |
| 858 A##B##_##C##_pre = LoadStorePreIndexFixed | D |
| 859 LOAD_STORE_OP_LIST(LOAD_STORE_PRE_INDEX) |
| 860 #undef LOAD_STORE_PRE_INDEX |
| 861 }; |
| 862 |
| 863 // Load/store unsigned offset. |
| 864 enum LoadStoreUnsignedOffset { |
| 865 LoadStoreUnsignedOffsetFixed = 0x39000000, |
| 866 LoadStoreUnsignedOffsetFMask = 0x3B000000, |
| 867 LoadStoreUnsignedOffsetMask = 0xFFC00000, |
| 868 PRFM_unsigned = LoadStoreUnsignedOffsetFixed | PRFM, |
| 869 #define LOAD_STORE_UNSIGNED_OFFSET(A, B, C, D) \ |
| 870 A##B##_##C##_unsigned = LoadStoreUnsignedOffsetFixed | D |
| 871 LOAD_STORE_OP_LIST(LOAD_STORE_UNSIGNED_OFFSET) |
| 872 #undef LOAD_STORE_UNSIGNED_OFFSET |
| 873 }; |
| 874 |
| 875 // Load/store register offset. |
| 876 enum LoadStoreRegisterOffset { |
| 877 LoadStoreRegisterOffsetFixed = 0x38200800, |
| 878 LoadStoreRegisterOffsetFMask = 0x3B200C00, |
| 879 LoadStoreRegisterOffsetMask = 0xFFE00C00, |
| 880 PRFM_reg = LoadStoreRegisterOffsetFixed | PRFM, |
| 881 #define LOAD_STORE_REGISTER_OFFSET(A, B, C, D) \ |
| 882 A##B##_##C##_reg = LoadStoreRegisterOffsetFixed | D |
| 883 LOAD_STORE_OP_LIST(LOAD_STORE_REGISTER_OFFSET) |
| 884 #undef LOAD_STORE_REGISTER_OFFSET |
| 885 }; |
| 886 |
| 887 // Conditional compare. |
| 888 enum ConditionalCompareOp { |
| 889 ConditionalCompareMask = 0x60000000, |
| 890 CCMN = 0x20000000, |
| 891 CCMP = 0x60000000 |
| 892 }; |
| 893 |
| 894 // Conditional compare register. |
| 895 enum ConditionalCompareRegisterOp { |
| 896 ConditionalCompareRegisterFixed = 0x1A400000, |
| 897 ConditionalCompareRegisterFMask = 0x1FE00800, |
| 898 ConditionalCompareRegisterMask = 0xFFE00C10, |
| 899 CCMN_w = ConditionalCompareRegisterFixed | CCMN, |
| 900 CCMN_x = ConditionalCompareRegisterFixed | SixtyFourBits | CCMN, |
| 901 CCMP_w = ConditionalCompareRegisterFixed | CCMP, |
| 902 CCMP_x = ConditionalCompareRegisterFixed | SixtyFourBits | CCMP |
| 903 }; |
| 904 |
| 905 // Conditional compare immediate. |
| 906 enum ConditionalCompareImmediateOp { |
| 907 ConditionalCompareImmediateFixed = 0x1A400800, |
| 908 ConditionalCompareImmediateFMask = 0x1FE00800, |
| 909 ConditionalCompareImmediateMask = 0xFFE00C10, |
| 910 CCMN_w_imm = ConditionalCompareImmediateFixed | CCMN, |
| 911 CCMN_x_imm = ConditionalCompareImmediateFixed | SixtyFourBits | CCMN, |
| 912 CCMP_w_imm = ConditionalCompareImmediateFixed | CCMP, |
| 913 CCMP_x_imm = ConditionalCompareImmediateFixed | SixtyFourBits | CCMP |
| 914 }; |
| 915 |
| 916 // Conditional select. |
| 917 enum ConditionalSelectOp { |
| 918 ConditionalSelectFixed = 0x1A800000, |
| 919 ConditionalSelectFMask = 0x1FE00000, |
| 920 ConditionalSelectMask = 0xFFE00C00, |
| 921 CSEL_w = ConditionalSelectFixed | 0x00000000, |
| 922 CSEL_x = ConditionalSelectFixed | 0x80000000, |
| 923 CSEL = CSEL_w, |
| 924 CSINC_w = ConditionalSelectFixed | 0x00000400, |
| 925 CSINC_x = ConditionalSelectFixed | 0x80000400, |
| 926 CSINC = CSINC_w, |
| 927 CSINV_w = ConditionalSelectFixed | 0x40000000, |
| 928 CSINV_x = ConditionalSelectFixed | 0xC0000000, |
| 929 CSINV = CSINV_w, |
| 930 CSNEG_w = ConditionalSelectFixed | 0x40000400, |
| 931 CSNEG_x = ConditionalSelectFixed | 0xC0000400, |
| 932 CSNEG = CSNEG_w |
| 933 }; |
| 934 |
| 935 // Data processing 1 source. |
| 936 enum DataProcessing1SourceOp { |
| 937 DataProcessing1SourceFixed = 0x5AC00000, |
| 938 DataProcessing1SourceFMask = 0x5FE00000, |
| 939 DataProcessing1SourceMask = 0xFFFFFC00, |
| 940 RBIT = DataProcessing1SourceFixed | 0x00000000, |
| 941 RBIT_w = RBIT, |
| 942 RBIT_x = RBIT | SixtyFourBits, |
| 943 REV16 = DataProcessing1SourceFixed | 0x00000400, |
| 944 REV16_w = REV16, |
| 945 REV16_x = REV16 | SixtyFourBits, |
| 946 REV = DataProcessing1SourceFixed | 0x00000800, |
| 947 REV_w = REV, |
| 948 REV32_x = REV | SixtyFourBits, |
| 949 REV_x = DataProcessing1SourceFixed | SixtyFourBits | 0x00000C00, |
| 950 CLZ = DataProcessing1SourceFixed | 0x00001000, |
| 951 CLZ_w = CLZ, |
| 952 CLZ_x = CLZ | SixtyFourBits, |
| 953 CLS = DataProcessing1SourceFixed | 0x00001400, |
| 954 CLS_w = CLS, |
| 955 CLS_x = CLS | SixtyFourBits |
| 956 }; |
| 957 |
| 958 // Data processing 2 source. |
| 959 enum DataProcessing2SourceOp { |
| 960 DataProcessing2SourceFixed = 0x1AC00000, |
| 961 DataProcessing2SourceFMask = 0x5FE00000, |
| 962 DataProcessing2SourceMask = 0xFFE0FC00, |
| 963 UDIV_w = DataProcessing2SourceFixed | 0x00000800, |
| 964 UDIV_x = DataProcessing2SourceFixed | 0x80000800, |
| 965 UDIV = UDIV_w, |
| 966 SDIV_w = DataProcessing2SourceFixed | 0x00000C00, |
| 967 SDIV_x = DataProcessing2SourceFixed | 0x80000C00, |
| 968 SDIV = SDIV_w, |
| 969 LSLV_w = DataProcessing2SourceFixed | 0x00002000, |
| 970 LSLV_x = DataProcessing2SourceFixed | 0x80002000, |
| 971 LSLV = LSLV_w, |
| 972 LSRV_w = DataProcessing2SourceFixed | 0x00002400, |
| 973 LSRV_x = DataProcessing2SourceFixed | 0x80002400, |
| 974 LSRV = LSRV_w, |
| 975 ASRV_w = DataProcessing2SourceFixed | 0x00002800, |
| 976 ASRV_x = DataProcessing2SourceFixed | 0x80002800, |
| 977 ASRV = ASRV_w, |
| 978 RORV_w = DataProcessing2SourceFixed | 0x00002C00, |
| 979 RORV_x = DataProcessing2SourceFixed | 0x80002C00, |
| 980 RORV = RORV_w, |
| 981 CRC32B = DataProcessing2SourceFixed | 0x00004000, |
| 982 CRC32H = DataProcessing2SourceFixed | 0x00004400, |
| 983 CRC32W = DataProcessing2SourceFixed | 0x00004800, |
| 984 CRC32X = DataProcessing2SourceFixed | SixtyFourBits | 0x00004C00, |
| 985 CRC32CB = DataProcessing2SourceFixed | 0x00005000, |
| 986 CRC32CH = DataProcessing2SourceFixed | 0x00005400, |
| 987 CRC32CW = DataProcessing2SourceFixed | 0x00005800, |
| 988 CRC32CX = DataProcessing2SourceFixed | SixtyFourBits | 0x00005C00 |
| 989 }; |
| 990 |
| 991 // Data processing 3 source. |
| 992 enum DataProcessing3SourceOp { |
| 993 DataProcessing3SourceFixed = 0x1B000000, |
| 994 DataProcessing3SourceFMask = 0x1F000000, |
| 995 DataProcessing3SourceMask = 0xFFE08000, |
| 996 MADD_w = DataProcessing3SourceFixed | 0x00000000, |
| 997 MADD_x = DataProcessing3SourceFixed | 0x80000000, |
| 998 MADD = MADD_w, |
| 999 MSUB_w = DataProcessing3SourceFixed | 0x00008000, |
| 1000 MSUB_x = DataProcessing3SourceFixed | 0x80008000, |
| 1001 MSUB = MSUB_w, |
| 1002 SMADDL_x = DataProcessing3SourceFixed | 0x80200000, |
| 1003 SMSUBL_x = DataProcessing3SourceFixed | 0x80208000, |
| 1004 SMULH_x = DataProcessing3SourceFixed | 0x80400000, |
| 1005 UMADDL_x = DataProcessing3SourceFixed | 0x80A00000, |
| 1006 UMSUBL_x = DataProcessing3SourceFixed | 0x80A08000, |
| 1007 UMULH_x = DataProcessing3SourceFixed | 0x80C00000 |
| 1008 }; |
| 1009 |
| 1010 // Floating point compare. |
| 1011 enum FPCompareOp { |
| 1012 FPCompareFixed = 0x1E202000, |
| 1013 FPCompareFMask = 0x5F203C00, |
| 1014 FPCompareMask = 0xFFE0FC1F, |
| 1015 FCMP_s = FPCompareFixed | 0x00000000, |
| 1016 FCMP_d = FPCompareFixed | FP64 | 0x00000000, |
| 1017 FCMP = FCMP_s, |
| 1018 FCMP_s_zero = FPCompareFixed | 0x00000008, |
| 1019 FCMP_d_zero = FPCompareFixed | FP64 | 0x00000008, |
| 1020 FCMP_zero = FCMP_s_zero, |
| 1021 FCMPE_s = FPCompareFixed | 0x00000010, |
| 1022 FCMPE_d = FPCompareFixed | FP64 | 0x00000010, |
| 1023 FCMPE_s_zero = FPCompareFixed | 0x00000018, |
| 1024 FCMPE_d_zero = FPCompareFixed | FP64 | 0x00000018 |
| 1025 }; |
| 1026 |
| 1027 // Floating point conditional compare. |
| 1028 enum FPConditionalCompareOp { |
| 1029 FPConditionalCompareFixed = 0x1E200400, |
| 1030 FPConditionalCompareFMask = 0x5F200C00, |
| 1031 FPConditionalCompareMask = 0xFFE00C10, |
| 1032 FCCMP_s = FPConditionalCompareFixed | 0x00000000, |
| 1033 FCCMP_d = FPConditionalCompareFixed | FP64 | 0x00000000, |
| 1034 FCCMP = FCCMP_s, |
| 1035 FCCMPE_s = FPConditionalCompareFixed | 0x00000010, |
| 1036 FCCMPE_d = FPConditionalCompareFixed | FP64 | 0x00000010, |
| 1037 FCCMPE = FCCMPE_s |
| 1038 }; |
| 1039 |
| 1040 // Floating point conditional select. |
| 1041 enum FPConditionalSelectOp { |
| 1042 FPConditionalSelectFixed = 0x1E200C00, |
| 1043 FPConditionalSelectFMask = 0x5F200C00, |
| 1044 FPConditionalSelectMask = 0xFFE00C00, |
| 1045 FCSEL_s = FPConditionalSelectFixed | 0x00000000, |
| 1046 FCSEL_d = FPConditionalSelectFixed | FP64 | 0x00000000, |
| 1047 FCSEL = FCSEL_s |
| 1048 }; |
| 1049 |
| 1050 // Floating point immediate. |
| 1051 enum FPImmediateOp { |
| 1052 FPImmediateFixed = 0x1E201000, |
| 1053 FPImmediateFMask = 0x5F201C00, |
| 1054 FPImmediateMask = 0xFFE01C00, |
| 1055 FMOV_s_imm = FPImmediateFixed | 0x00000000, |
| 1056 FMOV_d_imm = FPImmediateFixed | FP64 | 0x00000000 |
| 1057 }; |
| 1058 |
| 1059 // Floating point data processing 1 source. |
| 1060 enum FPDataProcessing1SourceOp { |
| 1061 FPDataProcessing1SourceFixed = 0x1E204000, |
| 1062 FPDataProcessing1SourceFMask = 0x5F207C00, |
| 1063 FPDataProcessing1SourceMask = 0xFFFFFC00, |
| 1064 FMOV_s = FPDataProcessing1SourceFixed | 0x00000000, |
| 1065 FMOV_d = FPDataProcessing1SourceFixed | FP64 | 0x00000000, |
| 1066 FMOV = FMOV_s, |
| 1067 FABS_s = FPDataProcessing1SourceFixed | 0x00008000, |
| 1068 FABS_d = FPDataProcessing1SourceFixed | FP64 | 0x00008000, |
| 1069 FABS = FABS_s, |
| 1070 FNEG_s = FPDataProcessing1SourceFixed | 0x00010000, |
| 1071 FNEG_d = FPDataProcessing1SourceFixed | FP64 | 0x00010000, |
| 1072 FNEG = FNEG_s, |
| 1073 FSQRT_s = FPDataProcessing1SourceFixed | 0x00018000, |
| 1074 FSQRT_d = FPDataProcessing1SourceFixed | FP64 | 0x00018000, |
| 1075 FSQRT = FSQRT_s, |
| 1076 FCVT_ds = FPDataProcessing1SourceFixed | 0x00028000, |
| 1077 FCVT_sd = FPDataProcessing1SourceFixed | FP64 | 0x00020000, |
| 1078 FRINTN_s = FPDataProcessing1SourceFixed | 0x00040000, |
| 1079 FRINTN_d = FPDataProcessing1SourceFixed | FP64 | 0x00040000, |
| 1080 FRINTN = FRINTN_s, |
| 1081 FRINTP_s = FPDataProcessing1SourceFixed | 0x00048000, |
| 1082 FRINTP_d = FPDataProcessing1SourceFixed | FP64 | 0x00048000, |
| 1083 FRINTP = FRINTP_s, |
| 1084 FRINTM_s = FPDataProcessing1SourceFixed | 0x00050000, |
| 1085 FRINTM_d = FPDataProcessing1SourceFixed | FP64 | 0x00050000, |
| 1086 FRINTM = FRINTM_s, |
| 1087 FRINTZ_s = FPDataProcessing1SourceFixed | 0x00058000, |
| 1088 FRINTZ_d = FPDataProcessing1SourceFixed | FP64 | 0x00058000, |
| 1089 FRINTZ = FRINTZ_s, |
| 1090 FRINTA_s = FPDataProcessing1SourceFixed | 0x00060000, |
| 1091 FRINTA_d = FPDataProcessing1SourceFixed | FP64 | 0x00060000, |
| 1092 FRINTA = FRINTA_s, |
| 1093 FRINTX_s = FPDataProcessing1SourceFixed | 0x00070000, |
| 1094 FRINTX_d = FPDataProcessing1SourceFixed | FP64 | 0x00070000, |
| 1095 FRINTX = FRINTX_s, |
| 1096 FRINTI_s = FPDataProcessing1SourceFixed | 0x00078000, |
| 1097 FRINTI_d = FPDataProcessing1SourceFixed | FP64 | 0x00078000, |
| 1098 FRINTI = FRINTI_s |
| 1099 }; |
| 1100 |
| 1101 // Floating point data processing 2 source. |
| 1102 enum FPDataProcessing2SourceOp { |
| 1103 FPDataProcessing2SourceFixed = 0x1E200800, |
| 1104 FPDataProcessing2SourceFMask = 0x5F200C00, |
| 1105 FPDataProcessing2SourceMask = 0xFFE0FC00, |
| 1106 FMUL = FPDataProcessing2SourceFixed | 0x00000000, |
| 1107 FMUL_s = FMUL, |
| 1108 FMUL_d = FMUL | FP64, |
| 1109 FDIV = FPDataProcessing2SourceFixed | 0x00001000, |
| 1110 FDIV_s = FDIV, |
| 1111 FDIV_d = FDIV | FP64, |
| 1112 FADD = FPDataProcessing2SourceFixed | 0x00002000, |
| 1113 FADD_s = FADD, |
| 1114 FADD_d = FADD | FP64, |
| 1115 FSUB = FPDataProcessing2SourceFixed | 0x00003000, |
| 1116 FSUB_s = FSUB, |
| 1117 FSUB_d = FSUB | FP64, |
| 1118 FMAX = FPDataProcessing2SourceFixed | 0x00004000, |
| 1119 FMAX_s = FMAX, |
| 1120 FMAX_d = FMAX | FP64, |
| 1121 FMIN = FPDataProcessing2SourceFixed | 0x00005000, |
| 1122 FMIN_s = FMIN, |
| 1123 FMIN_d = FMIN | FP64, |
| 1124 FMAXNM = FPDataProcessing2SourceFixed | 0x00006000, |
| 1125 FMAXNM_s = FMAXNM, |
| 1126 FMAXNM_d = FMAXNM | FP64, |
| 1127 FMINNM = FPDataProcessing2SourceFixed | 0x00007000, |
| 1128 FMINNM_s = FMINNM, |
| 1129 FMINNM_d = FMINNM | FP64, |
| 1130 FNMUL = FPDataProcessing2SourceFixed | 0x00008000, |
| 1131 FNMUL_s = FNMUL, |
| 1132 FNMUL_d = FNMUL | FP64 |
| 1133 }; |
| 1134 |
| 1135 // Floating point data processing 3 source. |
| 1136 enum FPDataProcessing3SourceOp { |
| 1137 FPDataProcessing3SourceFixed = 0x1F000000, |
| 1138 FPDataProcessing3SourceFMask = 0x5F000000, |
| 1139 FPDataProcessing3SourceMask = 0xFFE08000, |
| 1140 FMADD_s = FPDataProcessing3SourceFixed | 0x00000000, |
| 1141 FMSUB_s = FPDataProcessing3SourceFixed | 0x00008000, |
| 1142 FNMADD_s = FPDataProcessing3SourceFixed | 0x00200000, |
| 1143 FNMSUB_s = FPDataProcessing3SourceFixed | 0x00208000, |
| 1144 FMADD_d = FPDataProcessing3SourceFixed | 0x00400000, |
| 1145 FMSUB_d = FPDataProcessing3SourceFixed | 0x00408000, |
| 1146 FNMADD_d = FPDataProcessing3SourceFixed | 0x00600000, |
| 1147 FNMSUB_d = FPDataProcessing3SourceFixed | 0x00608000 |
| 1148 }; |
| 1149 |
| 1150 // Conversion between floating point and integer. |
| 1151 enum FPIntegerConvertOp { |
| 1152 FPIntegerConvertFixed = 0x1E200000, |
| 1153 FPIntegerConvertFMask = 0x5F20FC00, |
| 1154 FPIntegerConvertMask = 0xFFFFFC00, |
| 1155 FCVTNS = FPIntegerConvertFixed | 0x00000000, |
| 1156 FCVTNS_ws = FCVTNS, |
| 1157 FCVTNS_xs = FCVTNS | SixtyFourBits, |
| 1158 FCVTNS_wd = FCVTNS | FP64, |
| 1159 FCVTNS_xd = FCVTNS | SixtyFourBits | FP64, |
| 1160 FCVTNU = FPIntegerConvertFixed | 0x00010000, |
| 1161 FCVTNU_ws = FCVTNU, |
| 1162 FCVTNU_xs = FCVTNU | SixtyFourBits, |
| 1163 FCVTNU_wd = FCVTNU | FP64, |
| 1164 FCVTNU_xd = FCVTNU | SixtyFourBits | FP64, |
| 1165 FCVTPS = FPIntegerConvertFixed | 0x00080000, |
| 1166 FCVTPS_ws = FCVTPS, |
| 1167 FCVTPS_xs = FCVTPS | SixtyFourBits, |
| 1168 FCVTPS_wd = FCVTPS | FP64, |
| 1169 FCVTPS_xd = FCVTPS | SixtyFourBits | FP64, |
| 1170 FCVTPU = FPIntegerConvertFixed | 0x00090000, |
| 1171 FCVTPU_ws = FCVTPU, |
| 1172 FCVTPU_xs = FCVTPU | SixtyFourBits, |
| 1173 FCVTPU_wd = FCVTPU | FP64, |
| 1174 FCVTPU_xd = FCVTPU | SixtyFourBits | FP64, |
| 1175 FCVTMS = FPIntegerConvertFixed | 0x00100000, |
| 1176 FCVTMS_ws = FCVTMS, |
| 1177 FCVTMS_xs = FCVTMS | SixtyFourBits, |
| 1178 FCVTMS_wd = FCVTMS | FP64, |
| 1179 FCVTMS_xd = FCVTMS | SixtyFourBits | FP64, |
| 1180 FCVTMU = FPIntegerConvertFixed | 0x00110000, |
| 1181 FCVTMU_ws = FCVTMU, |
| 1182 FCVTMU_xs = FCVTMU | SixtyFourBits, |
| 1183 FCVTMU_wd = FCVTMU | FP64, |
| 1184 FCVTMU_xd = FCVTMU | SixtyFourBits | FP64, |
| 1185 FCVTZS = FPIntegerConvertFixed | 0x00180000, |
| 1186 FCVTZS_ws = FCVTZS, |
| 1187 FCVTZS_xs = FCVTZS | SixtyFourBits, |
| 1188 FCVTZS_wd = FCVTZS | FP64, |
| 1189 FCVTZS_xd = FCVTZS | SixtyFourBits | FP64, |
| 1190 FCVTZU = FPIntegerConvertFixed | 0x00190000, |
| 1191 FCVTZU_ws = FCVTZU, |
| 1192 FCVTZU_xs = FCVTZU | SixtyFourBits, |
| 1193 FCVTZU_wd = FCVTZU | FP64, |
| 1194 FCVTZU_xd = FCVTZU | SixtyFourBits | FP64, |
| 1195 SCVTF = FPIntegerConvertFixed | 0x00020000, |
| 1196 SCVTF_sw = SCVTF, |
| 1197 SCVTF_sx = SCVTF | SixtyFourBits, |
| 1198 SCVTF_dw = SCVTF | FP64, |
| 1199 SCVTF_dx = SCVTF | SixtyFourBits | FP64, |
| 1200 UCVTF = FPIntegerConvertFixed | 0x00030000, |
| 1201 UCVTF_sw = UCVTF, |
| 1202 UCVTF_sx = UCVTF | SixtyFourBits, |
| 1203 UCVTF_dw = UCVTF | FP64, |
| 1204 UCVTF_dx = UCVTF | SixtyFourBits | FP64, |
| 1205 FCVTAS = FPIntegerConvertFixed | 0x00040000, |
| 1206 FCVTAS_ws = FCVTAS, |
| 1207 FCVTAS_xs = FCVTAS | SixtyFourBits, |
| 1208 FCVTAS_wd = FCVTAS | FP64, |
| 1209 FCVTAS_xd = FCVTAS | SixtyFourBits | FP64, |
| 1210 FCVTAU = FPIntegerConvertFixed | 0x00050000, |
| 1211 FCVTAU_ws = FCVTAU, |
| 1212 FCVTAU_xs = FCVTAU | SixtyFourBits, |
| 1213 FCVTAU_wd = FCVTAU | FP64, |
| 1214 FCVTAU_xd = FCVTAU | SixtyFourBits | FP64, |
| 1215 FMOV_ws = FPIntegerConvertFixed | 0x00060000, |
| 1216 FMOV_sw = FPIntegerConvertFixed | 0x00070000, |
| 1217 FMOV_xd = FMOV_ws | SixtyFourBits | FP64, |
| 1218 FMOV_dx = FMOV_sw | SixtyFourBits | FP64 |
| 1219 }; |
| 1220 |
| 1221 // Conversion between fixed point and floating point. |
| 1222 enum FPFixedPointConvertOp { |
| 1223 FPFixedPointConvertFixed = 0x1E000000, |
| 1224 FPFixedPointConvertFMask = 0x5F200000, |
| 1225 FPFixedPointConvertMask = 0xFFFF0000, |
| 1226 FCVTZS_fixed = FPFixedPointConvertFixed | 0x00180000, |
| 1227 FCVTZS_ws_fixed = FCVTZS_fixed, |
| 1228 FCVTZS_xs_fixed = FCVTZS_fixed | SixtyFourBits, |
| 1229 FCVTZS_wd_fixed = FCVTZS_fixed | FP64, |
| 1230 FCVTZS_xd_fixed = FCVTZS_fixed | SixtyFourBits | FP64, |
| 1231 FCVTZU_fixed = FPFixedPointConvertFixed | 0x00190000, |
| 1232 FCVTZU_ws_fixed = FCVTZU_fixed, |
| 1233 FCVTZU_xs_fixed = FCVTZU_fixed | SixtyFourBits, |
| 1234 FCVTZU_wd_fixed = FCVTZU_fixed | FP64, |
| 1235 FCVTZU_xd_fixed = FCVTZU_fixed | SixtyFourBits | FP64, |
| 1236 SCVTF_fixed = FPFixedPointConvertFixed | 0x00020000, |
| 1237 SCVTF_sw_fixed = SCVTF_fixed, |
| 1238 SCVTF_sx_fixed = SCVTF_fixed | SixtyFourBits, |
| 1239 SCVTF_dw_fixed = SCVTF_fixed | FP64, |
| 1240 SCVTF_dx_fixed = SCVTF_fixed | SixtyFourBits | FP64, |
| 1241 UCVTF_fixed = FPFixedPointConvertFixed | 0x00030000, |
| 1242 UCVTF_sw_fixed = UCVTF_fixed, |
| 1243 UCVTF_sx_fixed = UCVTF_fixed | SixtyFourBits, |
| 1244 UCVTF_dw_fixed = UCVTF_fixed | FP64, |
| 1245 UCVTF_dx_fixed = UCVTF_fixed | SixtyFourBits | FP64 |
| 1246 }; |
| 1247 |
| 1248 // Unimplemented and unallocated instructions. These are defined to make fixed |
| 1249 // bit assertion easier. |
| 1250 enum UnimplementedOp { |
| 1251 UnimplementedFixed = 0x00000000, |
| 1252 UnimplementedFMask = 0x00000000 |
| 1253 }; |
| 1254 |
| 1255 enum UnallocatedOp { |
| 1256 UnallocatedFixed = 0x00000000, |
| 1257 UnallocatedFMask = 0x00000000 |
| 1258 }; |
| 1259 |
| 1260 } } // namespace v8::internal |
| 1261 |
| 1262 #endif // V8_A64_CONSTANTS_A64_H_ |
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