(mips) adding simulator support for AUI/DAUI/DAHI/DATI instructions.

src/mips64/assembler-mips64.cc

Index: src/mips64/assembler-mips64.cc
diff --git a/src/mips64/assembler-mips64.cc b/src/mips64/assembler-mips64.cc
index e0f12ed020f54f3102e95c73acfb599816adff98..7fc92b25a7ac398fceff3c8962b830bb0dae7aec 100644
--- a/src/mips64/assembler-mips64.cc
+++ b/src/mips64/assembler-mips64.cc
@@ -1954,7 +1954,7 @@ void Assembler::lui(Register rd, int32_t j) {
 }
 
 
-void Assembler::aui(Register rs, Register rt, int32_t j) {
+void Assembler::aui(Register rt, Register rs, int32_t j) {
   // This instruction uses same opcode as 'lui'. The difference in encoding is
   // 'lui' has zero reg. for rs field.
   DCHECK(!(rs.is(zero_reg)));

[balazs.kilvady, 2015/11/26 17:10:50]

The documantaison says 'In Release 6, LUI is an assembly idiom for AUI with
rs=0.' It does not mean rs cannot be zero_reg and lui must be used. Also the
above comment is not true completly. Do we need this restriction?
The same note/question for mips32. 

@@ -1963,8 +1963,9 @@ void Assembler::aui(Register rs, Register rt, int32_t j) {
 }
 
 
-void Assembler::daui(Register rs, Register rt, int32_t j) {
+void Assembler::daui(Register rt, Register rs, int32_t j) {
   DCHECK(is_uint16(j));
+  DCHECK(!rs.is(zero_reg));
   GenInstrImmediate(DAUI, rs, rt, j);
 }