Subzero. ARM32. Show FP lowering some love.

src/IceInstARM32.def

Index: src/IceInstARM32.def
diff --git a/src/IceInstARM32.def b/src/IceInstARM32.def
index b3d55b28385cfca213e75faf9979f28de62f76f3..2c06f9708b41ea2f5304f48d22ff94a19ac7991f 100644
--- a/src/IceInstARM32.def
+++ b/src/IceInstARM32.def
@@ -28,6 +28,9 @@
 // LR is not considered isInt to avoid being allocated as a register. It is
 // technically preserved, but save/restore is handled separately, based on
 // whether or not the function MaybeLeafFunc.
+//
+// The register tables can be generated using the gen_arm32_reg_tables.py
+// script.
 
 #define REGARM32_GPR_TABLE                                                     \
   /* val, encode, name, scratch,preserved,stackptr,frameptr,                   \
@@ -69,21 +72,6 @@
 //          isInt, isI64Pair, isFP32, isFP64, isVec128, alias_init)
 
 // S registers 0-15 are scratch, but 16-31 are preserved.
-// Regenerate this with the following python script:
-//
-// def print_sregs():
-//   for i in xrange(0, 32):
-//     is_scratch = 1 if i < 16 else 0
-//     is_preserved = 1 if i >= 16 else 0
-//     print ('  X(Reg_s{regnum:<2}, {regnum:<2}, "s{regnum}", ' +
-//            '{scratch}, {preserved}, 0, 0, 0, 0, 1, 0, 0, ' +
-//            'REGLIST2(RegARM32, d{regnum:<2}, ' +
-//            'q{regnum_q:<2}))    \\').format(
-//            regnum=i, regnum_d=i>>1,
-//            regnum_q=i>>2, scratch=is_scratch, preserved=is_preserved)
-//
-// print_sregs()
-//
 #define REGARM32_FP32_TABLE                                                    \
   /* val, encode, name, scratch,preserved,stackptr,frameptr,                   \
      isInt,isI64Pair,isFP32,isFP64,isVec128, alias_init */                     \
@@ -128,29 +116,6 @@
 // registers. In processors supporting the D32 feature this will effectively
 // cause double allocation to bias towards allocating "high" D registers, which
 // do not alias any S registers.
-//
-// Regenerate this with the following python script:
-// def print_dregs():
-//   for i in xrange(31, 15, -1):
-//     is_scratch = 1 if (i < 8 or i >= 16) else 0
-//     is_preserved = 1 if (8 <= i and i < 16) else 0
-//     print ('  X(Reg_d{regnum:<2}, {regnum:<2}, "d{regnum}", ' +
-//            '{scratch}, {preserved}, 0, 0, 0, 0, 0, 1, 0, ' +
-//            'REGLIST1(RegARM32, q{regnum_q:<2})    \\').format(
-//            regnum=i, regnum_q=i>>1, scratch=is_scratch,
-//            preserved=is_preserved)
-//   for i in xrange(15, -1, -1):
-//     is_scratch = 1 if (i < 8 or i >= 16) else 0
-//     is_preserved = 1 if (8 <= i and i < 16) else 0
-//     print ('  X(Reg_d{regnum:<2}, {regnum:<2}, "d{regnum}", ' +
-//            '{scratch}, {preserved}, 0, 0, 0, 0, 0, 1, 0, ' +
-//            'REGLIST3(RegARM32, s{regnum_s0:<2}, s{regnum_s1:<2}, ' +
-//            'q{regnum_q:<2}))   \\').format(
-//            regnum_s0 = (i<<1), regnum_s1 = (i<<1) + 1, regnum=i,
-//            regnum_q=i>>1, scratch=is_scratch, preserved=is_preserved)
-//
-// print_dregs()
-//
 #define REGARM32_FP64_TABLE                                                    \
   /* val, encode, name, scratch,preserved,stackptr,frameptr,                   \
      isInt,isI64Pair,isFP32,isFP64,isVec128, alias_init */                     \
@@ -192,31 +157,6 @@
 // Q registers 0-3 are scratch, 4-7 are preserved, and 8-15 are also scratch
 // (if supported by the D32 feature). Q registers are defined in reverse order
 // for the same reason as D registers.
-//
-// Regenerate this with the following python script:
-// def print_qregs():
-//   for i in xrange(15, 7, -1):
-//     is_scratch = 1 if (i < 4 or i >= 8) else 0
-//     is_preserved = 1 if (4 <= i and i < 8) else 0
-//     print ('  X(Reg_q{regnum:<2}, {regnum:<2}, "q{regnum}", ' +
-//            '{scratch}, {preserved}, 0, 0, 0, 0, 0, 0, 1, REGLIST2(' +
-//            'RegARM32, d{regnum_d0:<2}, d{regnum_d1:<2}))    \\').format(
-//            regnum_d0=(i<<1), regnum_d1=(i<<1)+1, regnum=i,
-//            scratch=is_scratch, preserved=is_preserved)
-//   for i in xrange(7, -1, -1):
-//     is_scratch = 1 if (i < 4 or i >= 8) else 0
-//     is_preserved = 1 if (4 <= i and i < 8) else 0
-//     print ('  X(Reg_q{regnum:<2}, {regnum:<2}, "q{regnum}", ' +
-//            '{scratch}, {preserved}, 0, 0, 0, 0, 0, 0, 1, REGLIST6(' +
-//            'RegARM32, s{regnum_s0:<2}, s{regnum_s1:<2}, ' +
-//            's{regnum_s2:<2}, s{regnum_s3:<2}, ' +
-//            'd{regnum_d0:<2}, d{regnum_d1:<2}))    \\').format(
-//            regnum_s0=(i<<2), regnum_s1=(i<<2)+1, regnum_s2=(i<<2)+2,
-//            regnum_s3=(i<<2)+3, regnum_d0=(i<<1), regnum_d1=(i<<1)+1,
-//            regnum=i, scratch=is_scratch, preserved=is_preserved)
-//
-// print_qregs()
-//
 #define REGARM32_VEC128_TABLE                                                  \
   /* val, encode, name, scratch, preserved, stackptr, frameptr,                \
      isInt, isI64Pair, isFP32, isFP64, isVec128, alias_init */                 \