Subzero. ARM32. Show FP lowering some love.

tests_lit/llvm2ice_tests/nacl-atomic-intrinsics.ll

 ; This tests each of the supported NaCl atomic instructions for every
 ; size allowed.
 
 ; RUN: %p2i -i %s --filetype=obj --disassemble --args -O2 \
 ; RUN:   -allow-externally-defined-symbols | FileCheck %s
 ; RUN: %p2i -i %s --filetype=obj --disassemble --args -O2 \
 ; RUN:   -allow-externally-defined-symbols | FileCheck --check-prefix=O2 %s
 ; RUN: %p2i -i %s --filetype=obj --disassemble --args -Om1 \
 ; RUN:   -allow-externally-defined-symbols | FileCheck %s
 
@@ skipping 1311 matching lines @@
 define internal i32 @test_atomic_is_lock_free(i32 %iptr) {
 entry:
   %ptr = inttoptr i32 %iptr to i8*
   %i = call i1 @llvm.nacl.atomic.is.lock.free(i32 4, i8* %ptr)
   %r = zext i1 %i to i32
   ret i32 %r
 }
 ; CHECK-LABEL: test_atomic_is_lock_free
 ; CHECK: mov {{.*}},0x1
 ; ARM32-LABEL: test_atomic_is_lock_free
-; ARM32: movw {{.*}}, #1
+; ARM32: mov {{.*}}, #1
 
 define internal i32 @test_not_lock_free(i32 %iptr) {
 entry:
   %ptr = inttoptr i32 %iptr to i8*
   %i = call i1 @llvm.nacl.atomic.is.lock.free(i32 7, i8* %ptr)
   %r = zext i1 %i to i32
   ret i32 %r
 }
 ; CHECK-LABEL: test_not_lock_free
 ; CHECK: mov {{.*}},0x0
@@ skipping 121 matching lines @@
   br i1 %cmp, label %done, label %body
 done:
   ret void
 }
 ; O2-LABEL: test_cmpxchg8b_regalloc
 ;;; eax and some other register will be used in the cmpxchg instruction.
 ; O2: lock cmpxchg8b QWORD PTR
 ;;; Make sure eax/ecx/edx/ebx aren't used again, e.g. as the induction variable.
 ; O2-NOT: {{eax|ecx|edx|ebx}}
 ; O2: pop ebx