Subzero. ARM32. Show FP lowering some love.

tests_lit/llvm2ice_tests/fp.convert.ll

 ; This tries to be a comprehensive test of f32 and f64 convert operations.
 ; The CHECK lines are only checking for basic instruction patterns
 ; that should be present regardless of the optimization level, so
 ; there are no special OPTM1 match lines.
 
 ; RUN: %p2i --filetype=obj --disassemble -i %s --args -O2 | FileCheck %s
 ; RUN: %p2i --filetype=obj --disassemble -i %s --args -Om1 | FileCheck %s
 
 ; RUN: %if --need=allow_dump --need=target_ARM32 --command %p2i --filetype=asm \
 ; RUN:   --target arm32 -i %s --args -O2 --skip-unimplemented \
@@ skipping 340 matching lines @@
 
 define internal double @signed32ToDoubleConst() {
 entry:
   %conv = sitofp i32 123 to double
   ret double %conv
 }
 ; CHECK-LABEL: signed32ToDoubleConst
 ; CHECK: cvtsi2sd {{.*[^1]}}
 ; CHECK: fld
 ; ARM32-LABEL: signed32ToDoubleConst
-; ARM32-DAG: movw [[CONST:r[0-9]+]], #123
+; ARM32-DAG: mov [[CONST:r[0-9]+]], #123
 ; ARM32-DAG: vmov [[SRC:s[0-9]+]], [[CONST]]
 ; ARM32-DAG: vcvt.f64.s32 {{d[0-9]+}}, [[SRC]]
 
 define internal float @signed32ToFloat(i32 %a) {
 entry:
   %conv = sitofp i32 %a to float
   ret float %conv
 }
 ; CHECK-LABEL: signed32ToFloat
 ; CHECK: cvtsi2ss
@@ skipping 216 matching lines @@
   %conv = bitcast i64 9035768 to double
   ret double %conv
 }
 ; CHECK-LABEL: int64BitcastToDoubleConst
 ; CHECK: mov
 ; ARM32-LABEL: int64BitcastToDoubleConst
 ; ARM32-DAG: movw [[REG0:r[0-9]+]], #57336
 ; ARM32-DAG: movt [[REG0]], #137
 ; ARM32-DAG: mov [[REG1:r[0-9]+]], #0
 ; ARM32-DAG: vmov d{{[0-9]+}}, [[REG0]], [[REG1]]