Subzero. ARM32. Show FP lowering some love.

src/IceTargetLoweringARM32.h

 //===- subzero/src/IceTargetLoweringARM32.h - ARM32 lowering ----*- C++ -*-===//
 //
 //                        The Subzero Code Generator
 //
 // This file is distributed under the University of Illinois Open Source
 // License. See LICENSE.TXT for details.
 //
 //===----------------------------------------------------------------------===//
 ///
 /// \file
@@ skipping 42 matching lines @@
   TargetARM32() = delete;
   TargetARM32(const TargetARM32 &) = delete;
   TargetARM32 &operator=(const TargetARM32 &) = delete;
 
 public:
   static void staticInit();
   // TODO(jvoung): return a unique_ptr.
   static TargetARM32 *create(Cfg *Func) { return new TargetARM32(Func); }
 
   void initNodeForLowering(CfgNode *Node) override {
-    BoolComputations.forgetProducers();
-    BoolComputations.recordProducers(Node);
-    BoolComputations.dump(Func);
+    Computations.forgetProducers();
+    Computations.recordProducers(Node);
+    Computations.dump(Func);
   }
 
   void translateOm1() override;
   void translateO2() override;
   bool doBranchOpt(Inst *I, const CfgNode *NextNode) override;
 
   SizeT getNumRegisters() const override { return RegARM32::Reg_NUM; }
   Variable *getPhysicalRegister(SizeT RegNum, Type Ty = IceType_void) override;
   IceString getRegName(SizeT RegNum, Type Ty) const override;
   llvm::SmallBitVector getRegisterSet(RegSetMask Include,
@@ skipping 715 matching lines @@
   void _vcmp(Variable *Src0, OperandARM32FlexFpZero *FpZero,
              CondARM32::Cond Pred = CondARM32::AL) {
     Context.insert(InstARM32Vcmp::create(Func, Src0, FpZero, Pred));
   }
   void _veor(Variable *Dest, Variable *Src0, Variable *Src1) {
     Context.insert(InstARM32Veor::create(Func, Dest, Src0, Src1));
   }
   void _vmrs(CondARM32::Cond Pred = CondARM32::AL) {
     Context.insert(InstARM32Vmrs::create(Func, Pred));
   }
+  void _vmla(Variable *Dest, Variable *Src0, Variable *Src1) {
+    Context.insert(InstARM32Vmla::create(Func, Dest, Src0, Src1));
+  }
+  void _vmls(Variable *Dest, Variable *Src0, Variable *Src1) {
+    Context.insert(InstARM32Vmls::create(Func, Dest, Src0, Src1));
+  }
   void _vmul(Variable *Dest, Variable *Src0, Variable *Src1) {
     Context.insert(InstARM32Vmul::create(Func, Dest, Src0, Src1));
   }
   void _vsqrt(Variable *Dest, Variable *Src,
               CondARM32::Cond Pred = CondARM32::AL) {
     Context.insert(InstARM32Vsqrt::create(Func, Dest, Src, Pred));
   }
   void _vsub(Variable *Dest, Variable *Src0, Variable *Src1) {
     Context.insert(InstARM32Vsub::create(Func, Dest, Src0, Src1));
   }
@@ skipping 201 matching lines @@
   size_t FixedAllocaSizeBytes = 0;
   size_t FixedAllocaAlignBytes = 0;
   bool PrologEmitsFixedAllocas = false;
   uint32_t MaxOutArgsSizeBytes = 0;
   // TODO(jpp): std::array instead of array.
   static llvm::SmallBitVector TypeToRegisterSet[RCARM32_NUM];
   static llvm::SmallBitVector RegisterAliases[RegARM32::Reg_NUM];
   static llvm::SmallBitVector ScratchRegs;
   llvm::SmallBitVector RegsUsed;
   VarList PhysicalRegisters[IceType_NUM];
+  VarList PreservedGPRs;
+  VarList PreservedSRegs;
 
   /// Helper class that understands the Calling Convention and register
   /// assignments. The first few integer type parameters can use r0-r3,
   /// regardless of their position relative to the floating-point/vector
   /// arguments in the argument list. Floating-point and vector arguments
   /// can use q0-q3 (aka d0-d7, s0-s15). For more information on the topic,
   /// see the ARM Architecture Procedure Calling Standards (AAPCS).
   ///
   /// Technically, arguments that can start with registers but extend beyond the
   /// available registers can be split between the registers and the stack.
@@ skipping 42 matching lines @@
   OperandARM32Mem *formAddressingMode(Type Ty, Cfg *Func, const Inst *LdSt,
                                       Operand *Base);
 
   void postambleCtpop64(const InstCall *Instr);
   void preambleDivRem(const InstCall *Instr);
   std::unordered_map<Operand *, void (TargetARM32::*)(const InstCall *Inst)>
       ARM32HelpersPreamble;
   std::unordered_map<Operand *, void (TargetARM32::*)(const InstCall *Inst)>
       ARM32HelpersPostamble;
 
-  class BoolComputationTracker {
+  class ComputationTracker {
   public:
-    BoolComputationTracker() = default;
-    ~BoolComputationTracker() = default;
+    ComputationTracker() = default;
+    ~ComputationTracker() = default;
 
     void forgetProducers() { KnownComputations.clear(); }
     void recordProducers(CfgNode *Node);
 
     const Inst *getProducerOf(const Operand *Opnd) const {
       auto *Var = llvm::dyn_cast<Variable>(Opnd);
       if (Var == nullptr) {
         return nullptr;
       }
 
@@ skipping 13 matching lines @@
       Str << "foldable producer:\n";
       for (const auto &Computation : KnownComputations) {
         Str << "    ";
         Computation.second.Instr->dump(Func);
         Str << "\n";
       }
       Str << "\n";
     }
 
   private:
-    class BoolComputationEntry {
+    class ComputationEntry {
     public:
-      explicit BoolComputationEntry(Inst *I) : Instr(I) {}
+      ComputationEntry(Inst *I, Type Ty) : Instr(I), ComputationType(Ty) {}
       Inst *const Instr;
       // Boolean folding is disabled for variables whose live range is multi
       // block. We conservatively initialize IsLiveOut to true, and set it to
       // false once we find the end of the live range for the variable defined
       // by this instruction. If liveness analysis is not performed (e.g., in
       // Om1 mode) IsLiveOut will never be set to false, and folding will be
       // disabled.
       bool IsLiveOut = true;
       int32_t NumUses = 0;
+      Type ComputationType;
     };
 
-    using BoolComputationMap = std::unordered_map<SizeT, BoolComputationEntry>;
-    BoolComputationMap KnownComputations;
+    // ComputationMap maps a Variable number to a payload identifying which
+    // instruction defined it.
+    using ComputationMap = std::unordered_map<SizeT, ComputationEntry>;
+    ComputationMap KnownComputations;
   };
 
-  BoolComputationTracker BoolComputations;
+  ComputationTracker Computations;
 
   // AllowTemporaryWithNoReg indicates if TargetARM32::makeReg() can be invoked
   // without specifying a physical register. This is needed for creating unbound
   // temporaries during Ice -> ARM lowering, but before register allocation.
   // This a safe-guard that no unbound temporaries are created during the
   // legalization post-passes.
   bool AllowTemporaryWithNoReg = true;
   // ForbidTemporaryWithoutReg is a RAII class that manages
   // AllowTemporaryWithNoReg.
   class ForbidTemporaryWithoutReg {
@@ skipping 52 matching lines @@
 
 private:
   ~TargetHeaderARM32() = default;
 
   TargetARM32Features CPUFeatures;
 };
 
 } // end of namespace Ice
 
 #endif // SUBZERO_SRC_ICETARGETLOWERINGARM32_H