Subzero. ARM32. Show FP lowering some love.

src/IceInstARM32.def

 //===- subzero/src/IceInstARM32.def - X-Macros for ARM32 insts --*- C++ -*-===//
 //
 //                        The Subzero Code Generator
 //
 // This file is distributed under the University of Illinois Open Source
 // License. See LICENSE.TXT for details.
 //
 //===----------------------------------------------------------------------===//
 //
 // This file defines properties of ARM32 instructions in the form of x-macros.
@@ skipping 10 matching lines @@
 // For the NaCl sandbox we also need to r9 (and the r8-r9 pair) for TLS, so
 // just reserve always.
 // TODO(jpp): Allow r9 to be isInt when sandboxing is turned off (native mode).
 //
 // IP is not considered isInt to reserve it as a scratch register. A scratch
 // register is useful for expanding instructions post-register allocation.
 //
 // LR is not considered isInt to avoid being allocated as a register. It is
 // technically preserved, but save/restore is handled separately, based on
 // whether or not the function MaybeLeafFunc.
+//
+// The register tables can be generated using the gen_arm32_reg_tables.py
+// script.
 
 #define REGARM32_GPR_TABLE                                                     \
   /* val, encode, name, scratch,preserved,stackptr,frameptr,                   \
      isInt,isI64Pair,isFP32,isFP64,isVec128, alias_init */                     \
   X(Reg_r0,   0, "r0",  1,0,0,0, 1,0,0,0,0, REGLIST1(RegARM32, r0r1))          \
   X(Reg_r1,   1, "r1",  1,0,0,0, 1,0,0,0,0, REGLIST1(RegARM32, r0r1))          \
   X(Reg_r2,   2, "r2",  1,0,0,0, 1,0,0,0,0, REGLIST1(RegARM32, r2r3))          \
   X(Reg_r3,   3, "r3",  1,0,0,0, 1,0,0,0,0, REGLIST1(RegARM32, r2r3))          \
   X(Reg_r4,   4, "r4",  0,1,0,0, 1,0,0,0,0, REGLIST1(RegARM32, r4r5))          \
   X(Reg_r5,   5, "r5",  0,1,0,0, 1,0,0,0,0, REGLIST1(RegARM32, r4r5))          \
@@ skipping 21 matching lines @@
   X(Reg_r0r1,   0, "r0, r1",  1,0,0,0, 0,1,0,0,0, REGLIST2(RegARM32, r0, r1))  \
   X(Reg_r2r3,   2, "r2, r3",  1,0,0,0, 0,1,0,0,0, REGLIST2(RegARM32, r2, r3))  \
   X(Reg_r4r5,   4, "r4, r5",  0,1,0,0, 0,1,0,0,0, REGLIST2(RegARM32, r4, r5))  \
   X(Reg_r6r7,   6, "r6, r7",  0,1,0,0, 0,1,0,0,0, REGLIST2(RegARM32, r6, r7))  \
   X(Reg_r8r9,   8, "r8, r9",  0,1,0,0, 0,0,0,0,0, REGLIST2(RegARM32, r8, r9))  \
   X(Reg_r10fp, 10, "r10, fp", 0,1,0,0, 0,0,0,0,0, REGLIST2(RegARM32, r10, fp))
 //#define X(val, encode, name, scratch, preserved, stackptr, frameptr,
 //          isInt, isI64Pair, isFP32, isFP64, isVec128, alias_init)
 
 // S registers 0-15 are scratch, but 16-31 are preserved.
-// Regenerate this with the following python script:
-//
-// def print_sregs():
-//   for i in xrange(0, 32):
-//     is_scratch = 1 if i < 16 else 0
-//     is_preserved = 1 if i >= 16 else 0
-//     print ('  X(Reg_s{regnum:<2}, {regnum:<2}, "s{regnum}", ' +
-//            '{scratch}, {preserved}, 0, 0, 0, 0, 1, 0, 0, ' +
-//            'REGLIST2(RegARM32, d{regnum:<2}, ' +
-//            'q{regnum_q:<2}))    \\').format(
-//            regnum=i, regnum_d=i>>1,
-//            regnum_q=i>>2, scratch=is_scratch, preserved=is_preserved)
-//
-// print_sregs()
-//
 #define REGARM32_FP32_TABLE                                                    \
   /* val, encode, name, scratch,preserved,stackptr,frameptr,                   \
      isInt,isI64Pair,isFP32,isFP64,isVec128, alias_init */                     \
   X(Reg_s0,   0, "s0",  1,0,0,0, 0,0,1,0,0, REGLIST2(RegARM32,  d0, q0))       \
   X(Reg_s1,   1, "s1",  1,0,0,0, 0,0,1,0,0, REGLIST2(RegARM32,  d0, q0))       \
   X(Reg_s2,   2, "s2",  1,0,0,0, 0,0,1,0,0, REGLIST2(RegARM32,  d1, q0))       \
   X(Reg_s3,   3, "s3",  1,0,0,0, 0,0,1,0,0, REGLIST2(RegARM32,  d1, q0))       \
   X(Reg_s4,   4, "s4",  1,0,0,0, 0,0,1,0,0, REGLIST2(RegARM32,  d2, q1))       \
   X(Reg_s5,   5, "s5",  1,0,0,0, 0,0,1,0,0, REGLIST2(RegARM32,  d2, q1))       \
   X(Reg_s6,   6, "s6",  1,0,0,0, 0,0,1,0,0, REGLIST2(RegARM32,  d3, q1))       \
@@ skipping 24 matching lines @@
   X(Reg_s31, 31, "s31", 0,1,0,0, 0,0,1,0,0, REGLIST2(RegARM32, d15, q7))
 //#define X(val, encode, name, scratch, preserved, stackptr, frameptr,
 //          isInt, isI64Pair, isFP32,isFP64, isVec128, alias_init)
 
 // D registers 0-7 are scratch, 8-15 are preserved, and 16-31 are also scratch
 // (if supported by the D32 feature vs D16). D registers are defined in reverse
 // order so that, during register allocation, Subzero will prefer higher D
 // registers. In processors supporting the D32 feature this will effectively
 // cause double allocation to bias towards allocating "high" D registers, which
 // do not alias any S registers.
-//
-// Regenerate this with the following python script:
-// def print_dregs():
-//   for i in xrange(31, 15, -1):
-//     is_scratch = 1 if (i < 8 or i >= 16) else 0
-//     is_preserved = 1 if (8 <= i and i < 16) else 0
-//     print ('  X(Reg_d{regnum:<2}, {regnum:<2}, "d{regnum}", ' +
-//            '{scratch}, {preserved}, 0, 0, 0, 0, 0, 1, 0, ' +
-//            'REGLIST1(RegARM32, q{regnum_q:<2})    \\').format(
-//            regnum=i, regnum_q=i>>1, scratch=is_scratch,
-//            preserved=is_preserved)
-//   for i in xrange(15, -1, -1):
-//     is_scratch = 1 if (i < 8 or i >= 16) else 0
-//     is_preserved = 1 if (8 <= i and i < 16) else 0
-//     print ('  X(Reg_d{regnum:<2}, {regnum:<2}, "d{regnum}", ' +
-//            '{scratch}, {preserved}, 0, 0, 0, 0, 0, 1, 0, ' +
-//            'REGLIST3(RegARM32, s{regnum_s0:<2}, s{regnum_s1:<2}, ' +
-//            'q{regnum_q:<2}))   \\').format(
-//            regnum_s0 = (i<<1), regnum_s1 = (i<<1) + 1, regnum=i,
-//            regnum_q=i>>1, scratch=is_scratch, preserved=is_preserved)
-//
-// print_dregs()
-//
 #define REGARM32_FP64_TABLE                                                    \
   /* val, encode, name, scratch,preserved,stackptr,frameptr,                   \
      isInt,isI64Pair,isFP32,isFP64,isVec128, alias_init */                     \
   X(Reg_d31, 31, "d31", 1,0,0,0, 0,0,0,1,0, REGLIST1(RegARM32, q15))           \
   X(Reg_d30, 30, "d30", 1,0,0,0, 0,0,0,1,0, REGLIST1(RegARM32, q15))           \
   X(Reg_d29, 29, "d29", 1,0,0,0, 0,0,0,1,0, REGLIST1(RegARM32, q14))           \
   X(Reg_d28, 28, "d28", 1,0,0,0, 0,0,0,1,0, REGLIST1(RegARM32, q14))           \
   X(Reg_d27, 27, "d27", 1,0,0,0, 0,0,0,1,0, REGLIST1(RegARM32, q13))           \
   X(Reg_d26, 26, "d26", 1,0,0,0, 0,0,0,1,0, REGLIST1(RegARM32, q13))           \
   X(Reg_d25, 25, "d25", 1,0,0,0, 0,0,0,1,0, REGLIST1(RegARM32, q12))           \
@@ skipping 21 matching lines @@
   X(Reg_d3,   3, "d3",  1,0,0,0, 0,0,0,1,0, REGLIST3(RegARM32, s6, s7, q1))    \
   X(Reg_d2,   2, "d2",  1,0,0,0, 0,0,0,1,0, REGLIST3(RegARM32, s4, s5, q1))    \
   X(Reg_d1,   1, "d1",  1,0,0,0, 0,0,0,1,0, REGLIST3(RegARM32, s2, s3, q0))    \
   X(Reg_d0,   0, "d0",  1,0,0,0, 0,0,0,1,0, REGLIST3(RegARM32, s0, s1, q0))
 //#define X(val, encode, name, scratch, preserved, stackptr, frameptr,
 //          isInt, isI64Pair, isFP32, isFP64, isVec128, alias_init)
 
 // Q registers 0-3 are scratch, 4-7 are preserved, and 8-15 are also scratch
 // (if supported by the D32 feature). Q registers are defined in reverse order
 // for the same reason as D registers.
-//
-// Regenerate this with the following python script:
-// def print_qregs():
-//   for i in xrange(15, 7, -1):
-//     is_scratch = 1 if (i < 4 or i >= 8) else 0
-//     is_preserved = 1 if (4 <= i and i < 8) else 0
-//     print ('  X(Reg_q{regnum:<2}, {regnum:<2}, "q{regnum}", ' +
-//            '{scratch}, {preserved}, 0, 0, 0, 0, 0, 0, 1, REGLIST2(' +
-//            'RegARM32, d{regnum_d0:<2}, d{regnum_d1:<2}))    \\').format(
-//            regnum_d0=(i<<1), regnum_d1=(i<<1)+1, regnum=i,
-//            scratch=is_scratch, preserved=is_preserved)
-//   for i in xrange(7, -1, -1):
-//     is_scratch = 1 if (i < 4 or i >= 8) else 0
-//     is_preserved = 1 if (4 <= i and i < 8) else 0
-//     print ('  X(Reg_q{regnum:<2}, {regnum:<2}, "q{regnum}", ' +
-//            '{scratch}, {preserved}, 0, 0, 0, 0, 0, 0, 1, REGLIST6(' +
-//            'RegARM32, s{regnum_s0:<2}, s{regnum_s1:<2}, ' +
-//            's{regnum_s2:<2}, s{regnum_s3:<2}, ' +
-//            'd{regnum_d0:<2}, d{regnum_d1:<2}))    \\').format(
-//            regnum_s0=(i<<2), regnum_s1=(i<<2)+1, regnum_s2=(i<<2)+2,
-//            regnum_s3=(i<<2)+3, regnum_d0=(i<<1), regnum_d1=(i<<1)+1,
-//            regnum=i, scratch=is_scratch, preserved=is_preserved)
-//
-// print_qregs()
-//
 #define REGARM32_VEC128_TABLE                                                  \
   /* val, encode, name, scratch, preserved, stackptr, frameptr,                \
      isInt, isI64Pair, isFP32, isFP64, isVec128, alias_init */                 \
   X(Reg_q15, 15, "q15", 1, 0, 0, 0, 0, 0, 0, 0, 1,                             \
     REGLIST2(RegARM32, d30, d31))                                              \
   X(Reg_q14, 14, "q14", 1, 0, 0, 0, 0, 0, 0, 0, 1,                             \
     REGLIST2(RegARM32, d28, d29))                                              \
   X(Reg_q13, 13, "q13", 1, 0, 0, 0, 0, 0, 0, 0, 1,                             \
     REGLIST2(RegARM32, d26, d27))                                              \
   X(Reg_q12, 12, "q12", 1, 0, 0, 0, 0, 0, 0, 0, 1,                             \
@@ skipping 104 matching lines @@
   X(LS, 9, HI, "ls")        /* unsigned lower or same */                       \
   X(GE, 10, LT, "ge")       /* signed greater than or equal */                 \
   X(LT, 11, GE, "lt")       /* signed less than */                             \
   X(GT, 12, LE, "gt")       /* signed greater than */                          \
   X(LE, 13, GT, "le")       /* signed less than or equal */                    \
   X(AL, 14, kNone, "")      /* always (unconditional) */                       \
   X(kNone, 15, kNone, "??") /* special condition / none */
 //#define X(tag, encode, opp, emit)
 
 #endif // SUBZERO_SRC_ICEINSTARM32_DEF