Fixes for integer division on ARM hardware so that assembler tests pass.

runtime/vm/constants_arm.h

Index: runtime/vm/constants_arm.h
===================================================================
--- runtime/vm/constants_arm.h	(revision 22334)
+++ runtime/vm/constants_arm.h	(working copy)
@@ -298,12 +298,27 @@
   kOffset12Bits = 12,
   kOffset12Mask = 0x00000fff,
 
-  // Mul instruction register fields encodings.
+  // Mul instruction register field encodings.
   kMulRdShift = 16,
   kMulRdBits = 4,
   kMulRnShift = 12,
   kMulRnBits = 4,
 
+  // Div instruction register field encodings.
+  kDivRdShift = 16,
+  kDivRdBits = 4,
+  kDivRmShift = 8,
+  kDivRmBits = 4,
+  kDivRnShift = 0,
+  kDivRnBits = 4,
+
+  // ldrex/strex register field encodings.
+  kLdExRnShift = 16,
+  kLdExRtShift = 12,
+  kStrExRnShift = 16,
+  kStrExRdShift = 12,
+  kStrExRtShift = 0,
+
   // MRC instruction offset field encoding.
   kCRmShift = 0,
   kCRmBits = 4,
@@ -449,6 +464,16 @@
     return bit_cast<double, uint64_t>(imm64);
   }
 
+  inline Register DivRdField() const {
+    return static_cast<Register>(Bits(kDivRdShift, kDivRdBits));
+  }
+  inline Register DivRmField() const {
+    return static_cast<Register>(Bits(kDivRmShift, kDivRmBits));
+  }
+  inline Register DivRnField() const {
+    return static_cast<Register>(Bits(kDivRnShift, kDivRnBits));
+  }
+
   // Test for data processing instructions of type 0 or 1.
   // See "ARM Architecture Reference Manual ARMv7-A and ARMv7-R edition",
   // section A5.1 "ARM instruction set encoding".