Fixes for integer division on ARM hardware so that assembler tests pass.

runtime/vm/constants_arm.h

 // Copyright (c) 2013, the Dart project authors.  Please see the AUTHORS file
 // for details. All rights reserved. Use of this source code is governed by a
 // BSD-style license that can be found in the LICENSE file.
 
 #ifndef VM_CONSTANTS_ARM_H_
 #define VM_CONSTANTS_ARM_H_
 
 #include "platform/assert.h"
 
 namespace dart {
@@ skipping 280 matching lines @@
   kShiftRegisterShift = 8,
   kShiftImmBits = 5,
   kShiftShift = 5,
   kShiftBits = 2,
 
   // Load/store instruction offset field encoding.
   kOffset12Shift = 0,
   kOffset12Bits = 12,
   kOffset12Mask = 0x00000fff,
 
-  // Mul instruction register fields encodings.
+  // Mul instruction register field encodings.
   kMulRdShift = 16,
   kMulRdBits = 4,
   kMulRnShift = 12,
   kMulRnBits = 4,
 
+  // Div instruction register field encodings.
+  kDivRdShift = 16,
+  kDivRdBits = 4,
+  kDivRmShift = 8,
+  kDivRmBits = 4,
+  kDivRnShift = 0,
+  kDivRnBits = 4,
+
   // MRC instruction offset field encoding.
   kCRmShift = 0,
   kCRmBits = 4,
   kOpc2Shift = 5,
   kOpc2Bits = 3,
   kCoprocShift = 8,
   kCoprocBits = 4,
   kCRnShift = 16,
   kCRnBits = 4,
   kOpc1Shift = 21,
@@ skipping 125 matching lines @@
     return bit_cast<float, uint32_t>(imm32);
   }
 
   // Field used in VFP double immediate move instruction
   inline double ImmDoubleField() const {
     uint64_t imm64 = (Bit(19)*(1LL << 63)) | (((1LL << 8) - Bit(18)) << 54) |
                      (Bits(16, 2)*(1LL << 52)) | (Bits(0, 4)*(1LL << 48));
     return bit_cast<double, uint64_t>(imm64);
   }
 
+  inline Register DivRdField() const {
+    return static_cast<Register>(Bits(kDivRdShift, kDivRdBits));
+  }
+  inline Register DivRmField() const {
+    return static_cast<Register>(Bits(kDivRmShift, kDivRmBits));
+  }
+  inline Register DivRnField() const {
+    return static_cast<Register>(Bits(kDivRnShift, kDivRnBits));
+  }
+
   // Test for data processing instructions of type 0 or 1.
   // See "ARM Architecture Reference Manual ARMv7-A and ARMv7-R edition",
   // section A5.1 "ARM instruction set encoding".
   inline bool IsDataProcessing() const {
     ASSERT(ConditionField() != kSpecialCondition);
     ASSERT(Bits(26, 2) == 0);  // Type 0 or 1.
     return ((Bits(20, 5) & 0x19) != 0x10) &&
       ((Bit(25) == 1) ||  // Data processing immediate.
        (Bit(4) == 0) ||  // Data processing register.
        (Bit(7) == 0));  // Data processing register-shifted register.
@@ skipping 105 matching lines @@
   static Instr* At(uword pc) { return reinterpret_cast<Instr*>(pc); }
 
  private:
   DISALLOW_ALLOCATION();
   DISALLOW_IMPLICIT_CONSTRUCTORS(Instr);
 };
 
 }  // namespace dart
 
 #endif  // VM_CONSTANTS_ARM_H_