Fixes for integer division on ARM hardware so that assembler tests pass.

runtime/vm/assembler_arm.cc

 // Copyright (c) 2013, the Dart project authors.  Please see the AUTHORS file
 // for details. All rights reserved. Use of this source code is governed by a
 // BSD-style license that can be found in the LICENSE file.
 
 #include "vm/globals.h"
 #if defined(TARGET_ARCH_ARM)
 
+// An extra check since we are assuming the existence of /proc/cpuinfo below.
+#if !defined(__linux__)
+#error ARM cross-compile only supported on Linux
+#endif

[regis, 2013/05/07 17:14:35]

Shoudn't it be
 #if !defined(USING_SIMULATOR) && !defined(__linux__)
otherwise, SIMARM will fail on Windows. I am not 100% sure we support it,
though, but we should.
In any case, you check /proc/cpuinfo only if !defined(USING_SIMULATOR).

[zra, 2013/05/07 17:50:18]

Done.

+
 #include "vm/assembler.h"
 #include "vm/simulator.h"
 #include "vm/runtime_entry.h"
 #include "vm/stub_code.h"
 
 namespace dart {
 
 DEFINE_FLAG(bool, print_stop_message, true, "Print stop message.");
 
 
 bool CPUFeatures::integer_division_supported_ = false;
 #if defined(DEBUG)
 bool CPUFeatures::initialized_ = false;
 #endif
 
 
 bool CPUFeatures::integer_division_supported() {
   DEBUG_ASSERT(initialized_);
   return integer_division_supported_;
 }
 
 
+// If we are using the simulator, allow tests to enable/disable support for
+// integer division.
 #if defined(USING_SIMULATOR)
 void CPUFeatures::set_integer_division_supported(bool supported) {
   integer_division_supported_ = supported;
 }
 #endif
 
 
-#define __ assembler.
+// Probe /proc/cpuinfo for features of the ARM processor.
+#if !defined(USING_SIMULATOR)
+static bool CPUInfoContainsString(const char* search_string) {
+  const char* file_name = "/proc/cpuinfo";
+  // This is written as a straight shot one pass parser
+  // and not using STL string and ifstream because,
+  // on Linux, it's reading from a (non-mmap-able)
+  // character special device.
+  FILE* f = NULL;
+  const char* what = search_string;
+
+  if (NULL == (f = fopen(file_name, "r")))
+    return false;
+
+  int k;
+  while (EOF != (k = fgetc(f))) {
+    if (k == *what) {
+      ++what;
+      while ((*what != '\0') && (*what == fgetc(f))) {
+        ++what;
+      }
+      if (*what == '\0') {
+        fclose(f);
+        return true;
+      } else {
+        what = search_string;
+      }
+    }
+  }
+  fclose(f);
+
+  // Did not find string in the proc file.
+  return false;
+}
+#endif
 
 void CPUFeatures::InitOnce() {
 #if defined(USING_SIMULATOR)
   integer_division_supported_ = true;
 #else
-  integer_division_supported_ = false;
+  ASSERT(CPUInfoContainsString("ARMv7"));  // Implements ARMv7.
+  ASSERT(CPUInfoContainsString("vfp"));  // Has floating point unit.
+  // Has integer division.
+  integer_division_supported_ = CPUInfoContainsString("idiva");
 #endif  // defined(USING_SIMULATOR)
 #if defined(DEBUG)
   initialized_ = true;
 #endif
 }
 
-#undef __
-
 
 // Instruction encoding bits.
 enum {
   H   = 1 << 5,   // halfword (or byte)
   L   = 1 << 20,  // load (or store)
   S   = 1 << 20,  // set condition code (or leave unchanged)
   W   = 1 << 21,  // writeback base register (or leave unchanged)
   A   = 1 << 21,  // accumulate in multiply instruction (or not)
   B   = 1 << 22,  // unsigned byte (or word)
   D   = 1 << 22,  // high/lo bit of start of s/d register range
@@ skipping 26 matching lines @@
   B24 = 1 << 24,
   B25 = 1 << 25,
   B26 = 1 << 26,
   B27 = 1 << 27,
 
   // ldrex/strex register field encodings.
   kLdExRnShift = 16,
   kLdExRtShift = 12,
   kStrExRnShift = 16,
   kStrExRdShift = 12,
   kStrExRtShift = 0,

[regis, 2013/05/07 17:14:35]

Unrelated to your change, but these ldrex/strex register field encodings should
be moved to constants_arm.h where other shift counts are declared.

[zra, 2013/05/07 17:50:18]

Done.

 };
 
 
 uint32_t Address::encoding3() const {
   if (kind_ == Immediate) {
     uint32_t offset = encoding_ & kOffset12Mask;
     ASSERT(offset < 256);
     return (encoding_ & ~kOffset12Mask) | B22 |
            ((offset & 0xf0) << 4) | (offset & 0xf);
   }
@@ skipping 375 matching lines @@
 
 void Assembler::EmitDivOp(Condition cond, int32_t opcode,
                           Register rd, Register rn, Register rm) {
   ASSERT(CPUFeatures::integer_division_supported());
   ASSERT(rd != kNoRegister);
   ASSERT(rn != kNoRegister);
   ASSERT(rm != kNoRegister);
   ASSERT(cond != kNoCondition);
   int32_t encoding = opcode |
     (static_cast<int32_t>(cond) << kConditionShift) |
-    (static_cast<int32_t>(rn) << kRnShift) |
-    (static_cast<int32_t>(rd) << kRdShift) |
+    (static_cast<int32_t>(rn) << kDivRnShift) |
+    (static_cast<int32_t>(rd) << kDivRdShift) |
     B26 | B25 | B24 | B20 | B4 |
-    (static_cast<int32_t>(rm) << kRmShift);
+    (static_cast<int32_t>(rm) << kDivRmShift);
   Emit(encoding);
 }
 
 
 void Assembler::sdiv(Register rd, Register rn, Register rm, Condition cond) {
   EmitDivOp(cond, 0, rd, rn, rm);
 }
 
 
 void Assembler::udiv(Register rd, Register rn, Register rm, Condition cond) {
@@ skipping 1620 matching lines @@
 
 const char* Assembler::FpuRegisterName(FpuRegister reg) {
   ASSERT((0 <= reg) && (reg < kNumberOfFpuRegisters));
   return fpu_reg_names[reg];
 }
 
 }  // namespace dart
 
 #endif  // defined TARGET_ARCH_ARM