Fixes for integer division on ARM hardware so that assembler tests pass.

runtime/vm/assembler_arm_test.cc

 // Copyright (c) 2013, the Dart project authors.  Please see the AUTHORS file
 // for details. All rights reserved. Use of this source code is governed by a
 // BSD-style license that can be found in the LICENSE file.
 
 #include "vm/globals.h"
 #if defined(TARGET_ARCH_ARM)
 
 #include "vm/assembler.h"
 #include "vm/os.h"
 #include "vm/unit_test.h"
@@ skipping 1371 matching lines @@
   EXPECT(test != NULL);
   typedef int (*Tst)();
   EXPECT_EQ(42, EXECUTE_TEST_CODE_INT32(Tst, test->entry()));
 }
 
 
 // Check that assembler mrc instruction encoding, and simulator decoding
 // are in agreement.
 #if defined(USING_SIMULATOR)
 ASSEMBLER_TEST_GENERATE(MrcHaveDiv, assembler) {
-  __ mrc(R0, 15, 0, 0, 2, 0);
+  __ mrc(R0, 15, 0, 0, 2, 0);  // Accesses ID_ISAR0.
+  // Bits 24 - 27 describe the presence of integer division. Bit 24 is set if
+  // it is available in the Thumb instruction set. Bit 25 is set if it is
+  // available both in Thumb and in the ARM instruction set.
   __ Lsr(R0, R0, 24);
   __ and_(R0, R0, ShifterOperand(0xf));
   __ mov(PC, ShifterOperand(LR));
 }
 
 
 ASSEMBLER_TEST_RUN(MrcHaveDiv, test) {
   EXPECT(test != NULL);
   typedef int (*Tst)();
   bool b = CPUFeatures::integer_division_supported();
   CPUFeatures::set_integer_division_supported(true);
-  EXPECT_LT(0, EXECUTE_TEST_CODE_INT32(Tst, test->entry()));
+  EXPECT_EQ(2, EXECUTE_TEST_CODE_INT32(Tst, test->entry()));
   CPUFeatures::set_integer_division_supported(b);
 }
 
 
 ASSEMBLER_TEST_GENERATE(MrcNoDiv, assembler) {
   __ mrc(R0, 15, 0, 0, 2, 0);
   __ Lsr(R0, R0, 24);
   __ and_(R0, R0, ShifterOperand(0xf));
   __ mov(PC, ShifterOperand(LR));
 }
 
 
 ASSEMBLER_TEST_RUN(MrcNoDiv, test) {
   EXPECT(test != NULL);
   typedef int (*Tst)();
   bool b = CPUFeatures::integer_division_supported();
   CPUFeatures::set_integer_division_supported(false);
   EXPECT_EQ(0, EXECUTE_TEST_CODE_INT32(Tst, test->entry()));
   CPUFeatures::set_integer_division_supported(b);
 }
-#endif  // defined(USING_SIMULATOR)
 
 
 ASSEMBLER_TEST_GENERATE(MrcReal, assembler) {
   __ mrc(R0, 15, 0, 0, 2, 0);
   __ Lsr(R0, R0, 24);
   __ and_(R0, R0, ShifterOperand(0xf));
   __ mov(PC, ShifterOperand(LR));
 }
 
 
 ASSEMBLER_TEST_RUN(MrcReal, test) {
   EXPECT(test != NULL);
   typedef int (*Tst)();
   bool have_div = CPUFeatures::integer_division_supported();
   int32_t r = EXECUTE_TEST_CODE_INT32(Tst, test->entry());
   if (have_div) {
-    EXPECT_LT(0, r);
+    EXPECT_EQ(2, r);
   } else {
     EXPECT_EQ(0, r);
   }
 }
+#endif  // defined(USING_SIMULATOR)
 
 
 ASSEMBLER_TEST_GENERATE(Udiv, assembler) {
-  __ mov(R0, ShifterOperand(27));
-  __ mov(R1, ShifterOperand(9));
-  __ udiv(R2, R0, R1);
-  __ Mov(R0, R2);
+  if (CPUFeatures::integer_division_supported()) {
+    __ mov(R0, ShifterOperand(27));
+    __ mov(R1, ShifterOperand(9));
+    __ udiv(R2, R0, R1);
+    __ Mov(R0, R2);
+  } else {
+    __ mov(R0, ShifterOperand(3));
+  }
   __ mov(PC, ShifterOperand(LR));
 }
 
 
 ASSEMBLER_TEST_RUN(Udiv, test) {
   EXPECT(test != NULL);
   typedef int (*Tst)();
   EXPECT_EQ(3, EXECUTE_TEST_CODE_INT32(Tst, test->entry()));
 }
 
 
 ASSEMBLER_TEST_GENERATE(Sdiv, assembler) {
-  __ mov(R0, ShifterOperand(27));
-  __ LoadImmediate(R1, -9);
-  __ sdiv(R2, R0, R1);
-  __ Mov(R0, R2);
+  if (CPUFeatures::integer_division_supported()) {
+    __ mov(R0, ShifterOperand(27));
+    __ LoadImmediate(R1, -9);
+    __ sdiv(R2, R0, R1);
+    __ Mov(R0, R2);
+  } else {
+    __ LoadImmediate(R0, -3);
+  }
   __ mov(PC, ShifterOperand(LR));
 }
 
 
 ASSEMBLER_TEST_RUN(Sdiv, test) {
   EXPECT(test != NULL);
   typedef int (*Tst)();
   EXPECT_EQ(-3, EXECUTE_TEST_CODE_INT32(Tst, test->entry()));
 }
 
 
 ASSEMBLER_TEST_GENERATE(Udiv_zero, assembler) {
-  __ mov(R0, ShifterOperand(27));
-  __ mov(R1, ShifterOperand(0));
-  __ udiv(R2, R0, R1);
-  __ Mov(R0, R2);
+  if (CPUFeatures::integer_division_supported()) {
+    __ mov(R0, ShifterOperand(27));
+    __ mov(R1, ShifterOperand(0));
+    __ udiv(R2, R0, R1);
+    __ Mov(R0, R2);
+  } else {
+    __ LoadImmediate(R0, 0);
+  }
   __ mov(PC, ShifterOperand(LR));
 }
 
 
 ASSEMBLER_TEST_RUN(Udiv_zero, test) {
   EXPECT(test != NULL);
   typedef int (*Tst)();
   EXPECT_EQ(0, EXECUTE_TEST_CODE_INT32(Tst, test->entry()));
 }
 
 
 ASSEMBLER_TEST_GENERATE(Sdiv_zero, assembler) {
-  __ mov(R0, ShifterOperand(27));
-  __ mov(R1, ShifterOperand(0));
-  __ udiv(R2, R0, R1);
-  __ Mov(R0, R2);
+  if (CPUFeatures::integer_division_supported()) {
+    __ mov(R0, ShifterOperand(27));
+    __ mov(R1, ShifterOperand(0));
+    __ udiv(R2, R0, R1);
+    __ Mov(R0, R2);
+  } else {
+    __ LoadImmediate(R0, 0);
+  }
   __ mov(PC, ShifterOperand(LR));
 }
 
 
 ASSEMBLER_TEST_RUN(Sdiv_zero, test) {
   EXPECT(test != NULL);
   typedef int (*Tst)();
   EXPECT_EQ(0, EXECUTE_TEST_CODE_INT32(Tst, test->entry()));
 }
 
 
 ASSEMBLER_TEST_GENERATE(Udiv_corner, assembler) {
-  __ LoadImmediate(R0, 0x80000000);
-  __ LoadImmediate(R1, 0xffffffff);
-  __ udiv(R2, R0, R1);
-  __ Mov(R0, R2);
+  if (CPUFeatures::integer_division_supported()) {
+    __ LoadImmediate(R0, 0x80000000);
+    __ LoadImmediate(R1, 0xffffffff);
+    __ udiv(R2, R0, R1);
+    __ Mov(R0, R2);
+  } else {
+    __ LoadImmediate(R0, 0);
+  }
   __ mov(PC, ShifterOperand(LR));
 }
 
 
 ASSEMBLER_TEST_RUN(Udiv_corner, test) {
   EXPECT(test != NULL);
   typedef int (*Tst)();
   EXPECT_EQ(0, EXECUTE_TEST_CODE_INT32(Tst, test->entry()));
 }
 
 
 ASSEMBLER_TEST_GENERATE(Sdiv_corner, assembler) {
-  __ LoadImmediate(R0, 0x80000000);
-  __ LoadImmediate(R1, 0xffffffff);
-  __ sdiv(R2, R0, R1);
-  __ Mov(R0, R2);
+  if (CPUFeatures::integer_division_supported()) {
+    __ LoadImmediate(R0, 0x80000000);
+    __ LoadImmediate(R1, 0xffffffff);
+    __ sdiv(R2, R0, R1);
+    __ Mov(R0, R2);
+  } else {
+    __ LoadImmediate(R0, 0x80000000);
+  }
   __ mov(PC, ShifterOperand(LR));
 }
 
 
 ASSEMBLER_TEST_RUN(Sdiv_corner, test) {
   EXPECT(test != NULL);
   typedef int (*Tst)();
   EXPECT_EQ(static_cast<int32_t>(0x80000000),
             EXECUTE_TEST_CODE_INT32(Tst, test->entry()));
 }
@@ skipping 26 matching lines @@
   __ StoreIntoObject(R2,
                      FieldAddress(R2, GrowableObjectArray::data_offset()),
                      R1);
   __ PopList((1 << CTX) | (1 << LR));
   __ Ret();
 }
 
 }  // namespace dart
 
 #endif  // defined TARGET_ARCH_ARM